A 105GOPS 36mm2 Heterogeneous SDR MPSoC with Energy-Aware Dynamic Scheduling and Iterative Detection-Decoding for 4G in 65nm CMOS

📋 论文概要

本文提出了一款面向4G通信的异构软件定义无线电（SDR）多处理器系统芯片（MPSoC），集成了多种处理单元，通过能量感知动态调度和迭代检测解码技术，在36mm2芯片面积内实现了105GOPS的峰值性能，有效解决了移动通信系统对灵活性与低功耗的冲突需求。

💡 主要创新点

• 提出了一种异构SDR MPSoC架构，结合多种处理器类型（如DSP、加速器）以兼顾灵活性和能效。
• 设计了能量感知动态调度策略，根据任务需求和功耗约束实时分配计算资源，降低整体能耗。
• 集成了迭代检测-解码机制，显著提升4G通信链路性能，同时支持多种传输模式。

🏷 关键词

📄 原文摘要

Erik Fischer, Steffen Kunze, Emil Matúš, Gerhard Fettweis, Holger Eisenreich, Georg Ellguth, Stephan Hartmann, Sebastian Höppner, Stefan Schiefer, Jens-Uwe Schlüßler, Stefan Scholze, Dennis Walter, René Schüffny Technische Universität Dresden, Dresden, Germany Modern mobile communication systems face conflicting design constraints. On the one hand, the expanding variety of transmission modes calls for highly flexible solutions supporting the ever-growing number and diversity of application requirements. On the other hand, stringent power restrictions (e.g., at femto base stations and terminals) must be considered, while satisfying the demanding performance requirements. In order to cope with these issues, existing SDR platforms, e.g. [1-2], propose an MPSoC with a heterogeneous array of processing elements (PEs). MPSoC solutions provide programmability and parallelism yielding flexibility, processing performance and power efficiency.

👥 作者与机构

Benedikt Noethen, Oliver Arnold, Esther Pérez Adeva, Tobias Seifert,