An 821MHz 7.9Gb/s 7.3pJ/b/iteration Charge-Recovery LDPC Decoder

📋 论文概要

本文提出了一款采用电荷恢复逻辑的576位LDPC解码器测试芯片，在65nm CMOS工艺中制造，集成了16个电感以回收门扇出电荷，实现高能效。芯片在自振荡821MHz时恢复51.4%的能量，吞吐量达7.9Gb/s，能效为7.3pJ/b/iteration，相比之前最大的电荷恢复逻辑芯片，器件数量提升了一个数量级。

💡 主要创新点

• 首次将电荷恢复逻辑应用于大规模LDPC解码器，通过集成电感回收门扇出电荷，显著降低能耗。
• 实现了比以往电荷恢复逻辑芯片大一个数量级的器件规模，验证了该技术在复杂数字电路中的可行性。
• 在821MHz高频下实现51.4%的能量回收率，同时保持7.9Gb/s的高吞吐量和7.3pJ/b/iteration的低能耗。

🏷 关键词

📄 原文摘要

This paper presents a 576b LDPC decoder test-chip designed using a chargerecovery logic family. The chip has been fabricated in a 65nm CMOS process and relies on 16 integrated inductors to achieve energy-efficient operation by recovering charge from gate fanouts. When self-oscillating at 821MHz, the chip recovers 51.4% of the energy supplied to it. In terms of device count, this chip is more than an order of magnitude larger than the largest previously-reported chips with charge-recovery logic [3-4]. When operating at 821MHz, it achieves a 7.9Gb/s throughput at 7.3pJ/b/iteration, improving on results in [1-2,5] by at least 1.7× in energy efficiency and 2.3× in area efficiency. Figure 27.6.1 shows the schematic of a two-input four-bit charge-recovery logic comparator used in this chip. Compared to other similar charge-recovery logic families [3], this so-called subthreshold boost logic (SBL) [4] can achieve higher

👥 作者与机构

Tai-Chuan Ou, Zhengya Zhang, Marios C. Papaefthymiou

University of Michigan, Ann Arbor, MI