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该论文提出了一种用于千兆以太网的全双工线路驱动器，采用轨到轨Class-AB输出级架构，在28nm CMOS工艺中实现。主要解决了传统线路驱动器在高电压电源下功耗高的问题，实现了全双工操作，降低了功耗。
standalone PHY chips with hundreds of millions of ports shipped every year. Transceiver design has recently focused on power reduction driven by the need for higher port density and throughput with minimum energy and thermal cost. The line drivers that deliver power from a high voltage supply to remote 100Ω differential loads dominate the GPHY power consumption. The supply voltage determined by the transmit amplitude specs (e.g., 2Vppdiff for 1000BASE-T/100BASE-TX Ethernet) does not scale with technology. This paper presents an architecture that enables rail-to-rail full-duplex operation for high voltage efficiency resulting in a 2.5V GPHY driver in 28nm CMOS that saves 24% power from the mainstream 3.3V drivers.
Hui Pan, Yuan Yao, Mostafa Hammad, Junhua Tan,
Karim Abdelhalim, Evelyn Wang, Rick Hsu, Jenny Yu, Joseph Aziz, Derek Tam, Ichiro Fujimori Broadcom, Irvine, CA Gigabit Ethernet PHY (GPHY) transceivers find wide use in SoCs and