60Gb/s NRZ and PAM4 Transmitters for 400GbE in 65nm CMOS

📋 论文概要

本文针对400GbE系统，在65nm CMOS工艺上实现了60Gb/s的NRZ和PAM4发射器，采用树形4:1复用器和60GHz PLL自适应相位对齐技术，解决了高速数据传输的带宽需求。

💡 主要创新点

• 在65nm CMOS中实现了60Gb/s的高速发射器，支持NRZ和PAM4两种调制方式。
• 采用树形4:1复用器结构，降低功耗和面积。
• 集成60GHz PLL和自适应相位对齐器，确保高速时钟同步。

🏷 关键词

📄 原文摘要

40Gb/s are practical to implement in CMOS technology [1]. However, next-generation datacom and telecom systems require transceivers to operate at even higher data rates. For example, a 400Gb/s Ethernet system may need 8×50Gb/s PAM2 (NRZ) or PAM4 channels [2]. This paper introduces fully integrated solutions for NRZ and PAM4 transmitters. The 60Gb/s operating speed demonstrates sufficient bandwidth even for standards with coding overhead. Figure 2.3.1 illustrates the NRZ transmitter architecture. It consists of a 4:1 multiplexer in a tree structure, a 60GHz PLL with adaptive phase aligner to optimize the clock phase in the last stage, and a built-in quarter-rate PRBS generator to facilitate testing. There are two independent modes to select the

👥 作者与机构

Ping-Chuan Chiang1,2, Hao-Wei Hung1, Hsiang-Yun Chu1,

Guan-Sing Chen1, Jri Lee1,2 National Taiwan University, Taipei, Taiwan, Atilia Technology, Taipei, Taiwan 1 2 Recent research indicates that data-link transceivers running at or below