A 21mW 15b 48MS/s Zero-Crossing Pipeline ADC in 0.13µm CMOS with 74dB SNDR

📋 论文概要

该论文提出了一种基于零交叉电路（ZCBC）的15位48MS/s流水线ADC，在0.13µm CMOS工艺中实现了74dB SNDR，功耗仅21mW。通过采用零交叉技术替代传统高增益运放，解决了低电压工艺下线性度与功耗难以兼顾的问题。

💡 主要创新点

• 采用零交叉电路（ZCBC）替代传统高增益运算放大器，在低电压CMOS工艺中实现高线性度与低功耗。
• 通过优化零交叉检测和电流源设计，在48MS/s采样率下达到15位分辨率，同时保持74dB SNDR。

🏷 关键词

📄 原文摘要

Kevin Guay2, Thomas Thurston2, Hae-Seung Lee3, Kush Gulati1, Matthew Straayer2 Maxim Integrated, San Jose, CA, Maxim Integrated, North Chelmsford, MA, 3 Massachusetts Institute of Technology, Cambridge, MA 1 2 Pipeline ADCs have traditionally served as a general-purpose architecture for high-speed and high-resolution applications such as medical and wireless receivers. Recently, achieving the highest levels of linearity with ultra-low power consumption has proven to be extremely challenging using modern CMOS technology with limited headroom. While zero-crossing-based circuits (ZCBC) have proven to be a power-efficient alternative to opamps in pipeline ADCs [1], performance using zero-crossing techniques have to-date only been demonstrated with ENOB ≤11. This paper presents a 15b 48MS/s zero-crossingbased pipeline ADC that achieves low power consumption of 99fJ/step and high linearity performance of 73.1dB SNDR and >80dB SFDR at Nyquist,

👥 作者与机构

Dong-Young Chang1, Carlos Muñoz2, Denis Daly2, Soon-Kyun Shin2,