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本文提出了一种16位3.2GS/s的电流舵DAC，采用65nm CMOS工艺，功耗仅240mW。该DAC在高达600MHz频率下实现了低于-80dBc的IM3线性度，满足了高级无线蜂窝基础设施系统对高光谱纯度和宽带宽的需求。
Govert Geelen, Harrie Gunnink, Yongjie Jin, Mustafa Kaba, Kerong Luo, Edward Paulus, Bang Pham, William Relyveld, Peter Zijlstra Integrated Device Technology, Eindhoven, The Netherlands Advanced wireless cellular infrastructure systems require DACs with high spectral purity over a wide bandwidth and which are fit for integration of multiple transmit channels with DSP. This calls for IM3 linearity better than -80dBc up to high frequencies and low power dissipation. In this paper, a high-speed currentsteering DAC is reported that combines low power and high linearity, enabled by a 3-dimensional sort-and-combine (3D-SC) calibration technique, CML switchdriving circuitry, and switch cascoding. It achieves similar linearity at significantly reduced power compared to a state-of-the-art high-linearity DAC [1] while its IM3 performance is more than 10dB better than the multi-GS/s lowpower DAC in [2]. The 16b 3.2GS/s DAC is implemented in a 65nm CMOS
Hans Van de Vel, Joost Briaire, Corné Bastiaansen, Pieter van Beek,