A 0.29mm2 Frequency Synthesizer in 40nm CMOS with 0.19psrms Jitter and <-100dBc Reference Spur for 802.11ac

📋 论文概要

该论文提出了一款面向802.11ac的分数-N频率合成器，通过多种技术同时实现了紧凑面积、低噪声和快速校准。解决了传统PLL中电荷泵和环路滤波器面积大、噪声高的问题。

💡 主要创新点

• 采用数字辅助技术减小环路滤波器和电荷泵面积，同时抑制带内噪声。
• 通过改进VCO谐振腔品质因数降低带外噪声，无需额外面积开销。
• 集成快速校准算法，支持256-QAM和MIMO应用。

🏷 关键词

📄 原文摘要

alldigital PLLs due to several substantial building blocks such as the loop filter and charge pump (CP). To achieve the required phase noise, the in-band noise is typically suppressed by increasing CP current and loop filter size, while the outof-band noise is reduced by improving VCO tank Q; both lead to increased die area. This paper presents a fractional-N synthesizer targeting the relatively stringent phase noise requirement to support 256-QAM and MIMO in 802.11ac. It deploys the following techniques to simultaneously address requirements of compact area, low noise and fast calibration: reuse of VCO inductor area for the loop filter; a PFD and CP design that relaxes CP design constraints without sacrificing noise; inductor-less LO generation for 802.11bgn mode; and an areaefficient reference clock doubler and associated

👥 作者与机构

Yu-Li Hsueh, Lan-Chou Cho, Chih-Hsien Shen, Yi-Chien Tsai,

Tzu-Chan Chueh, Tao-Yao Chang, Jui-Lin Hsu, Jing-Hong Conan Zhan MediaTek, Hsinchu, Taiwan Conventional analog PLLs do not scale well with process when compared to