A 1TOPS/W Analog Deep Machine-Learning Engine with Floating-Gate Storage in 0.13µm CMOS

📋 论文概要

提出一种采用浮栅存储的模拟深度机器学习引擎，在0.13µm CMOS工艺中实现了1TOPS/W的能效，解决了高维数据处理的功耗和维度灾难问题。

💡 主要创新点

• 采用模拟电路实现深度机器学习，利用浮栅存储非易失性权重，大幅降低功耗。
• 在0.13µm CMOS工艺中实现1TOPS/W的能效，远超数字实现。

🏷 关键词

📄 原文摘要

Direct processing of raw high-dimensional data such as images and video by machine learning systems is impractical both due to prohibitive power consumption and the “curse of dimensionality,” which makes learning tasks exponentially more difficult as dimension increases. Deep machine learning (DML) mimics the hierarchical presentation of information in the human brain to achieve robust automated feature extraction, reducing the dimension of such data. However, the computational complexity of DML systems limits large-scale implementations in standard digital computers. Custom analog or mixed-mode signal processors have been reported to yield much higher energy efficiency than DSP [1-4], presenting the means of overcoming these limitations. However, the use of volatile digital memory in [1-3] precludes their use in intermittentlypowered devices, and the required interfacing and internal A/D/A conversions

👥 作者与机构

Junjie Lu, Steven Young, Itamar Arel, Jeremy Holleman

University of Tennessee, Knoxville, TN