A 100MS/s 10.5b 2.46mW Comparator-less Pipeline ADC Using Self-Biased Ring Amplifiers

📋 论文概要

本文提出了一种无比较器的流水线ADC，采用自偏置环放大器替代传统OTA，实现了低功耗和低电压操作。该ADC在100MS/s采样率下达到10.5位精度，功耗仅2.46mW，解决了OTA功耗高和低电压设计困难的问题。

💡 主要创新点

• 引入自偏置环放大器，无需额外偏置电路，提高功耗效率和稳定性
• 消除比较器，简化电路并降低功耗，实现无比较器流水线架构

🏷 关键词

📄 原文摘要

Samsung Electronics, Yongin, Korea 1 2 Pipelined ADCs require accurate amplification; however traditional OTAs limit power efficiency since they require high quiescent current for slewing. In addition, it is difficult to design low-voltage OTAs in modern, scaled CMOS. The ring amplifier [1-4] provides an intriguing alternative to traditional OTAs. This work improves the power efficiency and practicality of the ring amplifier by introducing a self-biasing scheme and by eliminating the comparators. The ring amplifier is comprised of three inverter stages (Fig. 11.5.1(a)), stabilized in a feedback configuration. To prevent oscillation, [3] splits the second stage into two separately biased AC-coupled inverters. The bias voltages VRP and VRN are tuned to ensure that the 3rd-stage transistors MCP and MCN enter deep sub-threshold as VIN approaches the desired virtual ground voltage, so that the

👥 作者与机构

Yong Lim1,2, Michael P. Flynn1

University of Michigan, Ann Arbor, MI,