A 2.3GHz Fractional-N Dividerless Phase-Locked Loop with -112dBc/Hz In-Band Phase Noise

📋 论文概要

该论文提出了一种基于数字脉冲宽度调制器(DPWM)的无分频器分数N锁相环，解决了传统无分频器PLL只能工作在整数N模式的问题。通过调制参考信号的脉冲宽度，实现了2.3GHz的分数N频率合成，并达到了-112dBc/Hz的带内相位噪声。

💡 主要创新点

• 首次提出使用数字脉冲宽度调制器(DPWM)实现无分频器PLL的分数N操作，突破了只能整数N的限制。
• 在2.3GHz载波频率下实现-112dBc/Hz的极低带内相位噪声，性能优于传统架构。

🏷 关键词

📄 原文摘要

Recently, dividerless PLL architectures, including sub-sampling PLLs [1] and injection-locked PLLs [2], have been reported to achieve superior phase noise with respect to conventional PLL architectures. However, these dividerless architectures can only be operated in integer-N mode inherently. In order to operate in fractional-N mode, this work proposes a digital pulse-width modulator (DPWM) to modulate the pulse width of the input reference signal to synthesize the output frequency. The block diagram of the proposed dividerless fractional-N PLL is shown in Fig. 21.2.1. The core circuit is a sub-sampling phase-locked loop (SSPLL) because it not only achieves a higher phase-to-current gain but also introduces no noise on the feedback divider. The sub-sampling-based PD (SSPD) directly samples the differential sinusoidal outputs of the VCO by the clock generated by the proposed DPWM. The sampler generates Vsam,up and Vsam,dn to control the charge

👥 作者与机构

Po-Chun Huang, Wei-Sung Chang, Tai-Cheng Lee

National Taiwan University, Taipei, Taiwan