⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种自适应时钟系统，用于应对高性能微处理器中因负载变化导致的电源电压波动问题。通过动态调整时钟频率，该系统减少了传统设计中为应对电压波动而预留的10-15%电压裕量，从而在28nm x86-64微处理器上显著提升了能效。
In high-performance microprocessor cores, the on-die supply voltage seen by the transistors is non-ideal and exhibits significant fluctuations. These supply fluctuations are caused by sudden changes in the current consumed by the microprocessor in response to variations in workloads. This non-ideal supply can cause performance degradation or functional failures. Therefore, a significant amount of margin (10-15%) needs to be added to the ideal voltage (if there were no AC voltage variations) to ensure that the processor always executes correctly at the committed voltage-frequency points. This excess voltage wastes power proportional to the square of the voltage increase. Several techniques have been proposed and implemented either to mitigate or compensate for supply noise. The techniques include the following: (1) Improving the supply network impedance by addition of decoupling capacitance
Aaron Grenat1, Sanjay Pant1, Ravinder Rachala1, Samuel Naffziger2
AMD, Austin, TX, 2AMD, Fort Collins, CO