A 25Gb/s 5.8mW CMOS Equalizer

📋 论文概要

本文提出了一种半速率25Gb/s CMOS均衡器，功耗仅5.8mW，效率达0.232mW/Gb/s，远低于1mW/Gb/s的常规目标。通过采用电荷转向技术，解决了高速率下功率-速度权衡的挑战，适用于100GbE等多通道接收机。

💡 主要创新点

• 采用电荷转向技术实现低功耗均衡器，显著降低功耗。
• 半速率架构设计，在25Gb/s速率下实现5.8mW超低功耗。

🏷 关键词

📄 原文摘要

The power consumption of broadband receivers becomes particularly critical in multi-lane applications such as the 100 Gigabit Ethernet. However, the powerspeed trade-off tends to intensify at higher rates, making it a greater challenge to reach the generally-accepted efficiency of 1mW/Gb/s. Prominent among the power-hungry receiver building blocks are the clock-and-data-recovery circuit, the deserializer, and the front-end equalizer. The use of charge-steering techniques has shown promise for the low-power implementation of the first two functions [1]. This paper introduces a half-rate 25Gb/s equalizer employing charge steering and achieving an efficiency of 0.232mW/Gb/s. In addition to dealing with the generic delay bounds in direct or unrolled decision-feedback equalizers (DFEs), our architecture must also accommodate the return-to-zero (RZ) format inherent in certain charge-steering topologies [1].

👥 作者与机构

Jun Won Jung, Behzad Razavi

University of California, Los Angeles, CA