28Gb/s 560mW Multi-Standard SerDes with SingleStage Analog Front-End and 14-Tap DecisionFeedback Equalizer in 28nm CMOS

📋 论文概要

提出一种28Gb/s 560mW的多标准SerDes，采用单级模拟前端和14抽头判决反馈均衡器，支持OIF CEI-25G-LR等多种高速标准，解决了高速率下的均衡和功耗挑战。

💡 主要创新点

• 采用单级模拟前端结构，降低功耗和复杂度
• 14抽头判决反馈均衡器实现高符号间干扰抑制
• 支持多标准（CEI-25G-LR, CEI-28G-MR/SR/VSR等）的灵活设计

📄 原文摘要

Hairong Gao, Ping Jing, Gary Hom, Anshi Liang, Eric Zhang, Aniket Kadkol, Ruchi Kothari, Gordon Chan, Yehui Sun, Benjamin Ge, Jason Zeng, Kathy Ling, Michael Wang, Amaresh Malipatil, Shiva Kotagiri, Lijun Li, Chris Abel, Freeman Zhong LSI, San Jose, CA A high-speed SerDes must meet multiple challenges including high-speed operation, intensive equalization technique, low power consumption, small area and robustness. In order to meet new standards, such a OIF CEI-25G-LR, CEI28G-MR/SR/VSR, IEEE802.3bj and 32G-FC, data-rates are increased to 25 to 28Gb/s, which is more than 75% higher than the previous generation of SerDes. For SerDes applications with several hundreds of lanes integrated in single chip, power consumption is very important factor while maintaining high performance. There are several previous works at 28Gb/s or higher data-rate [12]. They use an unrolled DFE to meet the critical timing margin, but the unrolled

👥 作者与机构

Hiroshi Kimura, Pervez Aziz, Tai Jing, Ashutosh Sinha, Ram Narayan,