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该论文提出了一种在0.6V低电压下工作的70MHz四阶连续时间巴特沃斯滤波器，通过时间域信号处理技术解决了低电压下模拟电路信噪比和线性度下降的问题，实现了55.8dB SNR和60dB THD。
Jayanth N. Kuppambatti, Baradwaj Vigraham, Peter R. Kinget Columbia University, New York, NY Technology scaling is leading to supply voltage reduction and shrinking voltage headroom, making it very challenging for analog circuits to achieve high signalto-noise-and-distortion ratios (SNDRs). For example, at Vdd ≤ 0.6V, the peak signal swing is 30% of Vdd in [1]-[3]. Since timing accuracy is improving in nanoscale CMOS, techniques have been proposed representing analog information in the time or phase domain. However, the linearity of the transformation between time or phase domain and the voltage or current domain remains a bottleneck at low supply voltages. In [2], ring-oscillator based integrators replace conventional OTA-based integrators, but the output signal swing is still limited to 30% of Vdd by the voltage headroom of the charge pump, which performs phase-to-voltage conversion. We propose switched-mode
Filter with 55.8dB SNR, 60dB THD at +2.8dBm Output, Signal Power