ISSCC 2014
Session 8
Wireline I/O
A 12×5 Two-Dimensional Optical I/O Array for 600Gb/s Chip-to-Chip Interconnect in 65nm CMOS
The aggregate bandwidth required between two processors, for example, is expected to extend into the terabit-per-second range or higher [1]. Bandwidth is typically the bottleneck in such situations. Optical interconnect
ISSCC 2014
Session 8
Wireline I/O
A 6Gb/s Transceiver with a Nonlinear Electronic Dispersion Compensator for Directly Modulated Distributed-Feedback Lasers
medium-reach optical links due to its cost effectiveness. However, DMLs are not appropriate for use in fiber links longer than 20km at 6Gb/s or equivalent, because the SNR penalty increases abruptly due to excessive chro
ISSCC 2014
Session 2
Wireline I/O
A Background Calibration Technique to Control Bandwidth in Digital PLLs
parameters that are subject to process, temperature and voltage spreads, as well as to variations along the frequency-tuning range. Even in digital PLLs, which rely on a digital loop filter, the bandwidth still depends o
ISSCC 2014
Session 2
Wireline I/O
A Pulse-Position-Modulation Phase-Noise-Reduction Technique for a 2-to-16GHz Injection-Locked Ring Oscillator in 20nm CMOS
Wayne Fang2, Ali M. Niknejad1, Jafar Savoj2, Ken Chang2 University of California, Berkeley, CA, Xilinx, San Jose, CA 1 2 High-speed transceivers embedded inside FPGAs require softwareprogrammable clocking circuits to cov
ISSCC 2014
Session 2
Wireline I/O
A Coefficient-Error-Robust FFE TX with 230% EyeVariation Improvement Without Calibration in 65nm CMOS Technology
(FFE) transmitter (TX) for massively parallel links. Recently, massively parallel links such as on-chip links [1-3], silicon interposers [4,5], or wide I/Os [6] are gaining popularity to meet increasing demand for data t
ISSCC 2014
Session 2
Wireline I/O
A 5.67mW 9Gb/s DLL-Based Reference-less CDR with Pattern-Dependent Clock-Embedded Signaling for Intra-Panel Interface
Samsung Electronics, Yongin, Korea 1 2 Point-to-point data transmission with clock-embedded signaling (CES) has been generally adopted in intra-panel interfaces, which need to support fine resolution, high frame rate, an
ISSCC 2014
Session 2
Wireline I/O
A 0.25pJ/b 0.7V 16Gb/s 3-Tap Decision-Feedback Equalizer in 65nm CMOS
Texas A&M University, College Station, TX, 3 Fudan University, Shanghai, China 1 2 Supply-voltage scaling has become one of the most effective methods to improve the energy efficiency of power-constrained systems, motiva
ISSCC 2014
Session 2
Wireline I/O
A 25Gb/s 5.8mW CMOS Equalizer
The power consumption of broadband receivers becomes particularly critical in multi-lane applications such as the 100 Gigabit Ethernet. However, the powerspeed trade-off tends to intensify at higher rates, making it a gr
ISSCC 2014
Session 2
Wireline I/O
60Gb/s NRZ and PAM4 Transmitters for 400GbE in 65nm CMOS
40Gb/s are practical to implement in CMOS technology [1]. However, next-generation datacom and telecom systems require transceivers to operate at even higher data rates. For example, a 400Gb/s Ethernet system may need 8×
ISSCC 2014
Session 2
Wireline I/O
A 780mW 4×28Gb/s Transceiver for 100GbE Gearbox PHY in 40nm CMOS
centers and network operators to support data-rich services like video streaming and social media. This has accelerated the adoption of 100Gb/s connectivity from the present 10Gb/s and 40Gb/s rates. One challenge that re
ISSCC 2014
Session 2
Wireline I/O
28Gb/s 560mW Multi-Standard SerDes with SingleStage Analog Front-End and 14-Tap DecisionFeedback Equalizer in 28nm CMOS
Hairong Gao, Ping Jing, Gary Hom, Anshi Liang, Eric Zhang, Aniket Kadkol, Ruchi Kothari, Gordon Chan, Yehui Sun, Benjamin Ge, Jason Zeng, Kathy Ling, Michael Wang, Amaresh Malipatil, Shiva Kotagiri, Lijun Li, Chris Abel,
ISSCC 2013
Session 7
Wireline I/O
A 10Gb/s 6Vpp Differential Modulator Driver in 0.18µm SiGe-BiCMOS
ISSCC 2013
Session 7
Wireline I/O
Optical Receivers Using DFE-IIR Equalization
Future computing systems will require increasingly high bandwidth to supply data to microprocessors, FPGAs, and other computational blocks [1,2]. Increasing data rate is a common solution, as I/O pad density is not scali
ISSCC 2013
Session 7
Wireline I/O
A 20Gb/s NRZ/PAM-4 1V Transmitter in 40nm CMOS Driving a Si-Photonic Modulator in 0.13µm CMOS
Sanjay Sunder2, Jan Van der Spiegel1, Yifan Wang2, Mark Webster2, Will Wilson2 because a smaller inverter can be used for a reduced segment capacitance, and the effective capacitance is also reduced since not all segment
ISSCC 2013
Session 7
Wireline I/O
A 1.23pJ/b 2.5Gb/s Monolithically Integrated Optical Carrier-Injection Ring Modulator and All-Digital Driver Circuit in Commercial 45nm SOI
Jason S. Orcutt1, Jonathan C. Leu1, Mark Wade2, Yu-Hsin Chen1, Kareem Nammari2, Xiaoxi Wang1, Hanqing Li1, Rajeev Ram1, Milos A. Popovic2, Vladimir Stojanovic1 Massachusetts Institute of Technology, Cambridge, MA, Univer
ISSCC 2013
Session 7
Wireline I/O
A Ring-Resonator-Based Silicon Photonics Transceiver with Bias-Based Wavelength Stabilization and Adaptive-Power-Sensitivity Receiver ratio at the input wavelength of 1286.93nm. The maximum tuning power is 425μW for a resonance range of 0.22nm, which can be leveraged as a fine-control in a dual thermal/bias tuning scheme to improve overall tuning efficiency.
Chao Ma2, Chin-Hui Chen3, Zhen Peng3, Marco Fiorentino3, Patrick Chiang2,4, Samuel Palermo1 1 2 1 1 1 Texas A&M University, College Station, TX, Oregon State University, Corvallis, OR, 3 Hewlett Packard, Palo Alto, CA, 4
ISSCC 2013
Session 7
Wireline I/O
A Blind Baud-Rate ADC-Based CDR
ter tolerance degradation in one of two ways. First, clock skew would appear effectively as high-frequency periodic jitter. Second, the interleaved I&D blocks would experience a gain mismatch because the integration is p
ISSCC 2013
Session 7
Wireline I/O
100Gb/s Ethernet Chipsets in 65nm CMOS Technology
Note that ISS is properly biased by constant IR circuit, whose on-chip resistor experiences the same variation as RD does. With RB and CB providing unaltered bias point to M2, signal current Iin flows through RF and curr
ISSCC 2013
Session 7
Wireline I/O
A 4× 25-to-28Gb/s 4.9mW/Gb/s -9.7dBm HighSensitivity Optical Receiver Based on 65nm CMOS for Board-to-Board Interconnects
[4]. The developed TIA (with an offset canceller) reduces peak-to-peak current variations due to offset voltage by 96%. Moreover, I PrA n,rms is reduced from 3.5μArms to 2.6μArms by increasing ZPrA. With an increase in t
ISSCC 2013
Session 7
Wireline I/O
A Quad 25Gb/s 270mW TIA in 0.13µm BiCMOS with <0.15dB Crosstalk Penalty
Finisar, Sunnyvale, CA The push for 100Gb/s optical transport and beyond necessitates electronic components at higher speed and integration level in order to drive down cost, complexity and size of transceivers [1-2]. Th
ISSCC 2013
Session 2
Wireline I/O
A 0.94mW/Gb/s 22Gb/s 2-Tap Partial-Response DFE Receiver in 40nm LP CMOS
A decision-feedback equalizer (DFE) reconstructs the post-cursor inter-symbol interference (ISI) pattern from the detected data sequence and subtracts it from the received signal before detecting the next symbol. Therefo
ISSCC 2013
Session 2
Wireline I/O
32Gb/s 28nm CMOS Time-Interleaved Transmitter Compatible with NRZ Receiver with DFE
Fujitsu, Kawasaki, Japan, 4 Fujitsu Microelectronics Solutions, Akiruno, Japan Since the transmitter uses 4-way interleaved quarter-rate clocking to generate the output signal, the output signal integrity is prone to dut
ISSCC 2013
Session 2
Wireline I/O
A 32-to-48Gb/s Serializing Transmitter Using Multiphase Sampling in 65nm CMOS
Serial-link transmitters are widely used in applications like optical transceivers and multi-gigabit Ethernet. At tens of Gb/s, the operating range of bit-rates is narrow; limited by the speed of the multiplexing and the
ISSCC 2013
Session 2
Wireline I/O
32Gb/s Data-Interpolator Receiver with 2-Tap DFE in 28nm CMOS
Win Chaivipas1, Takushi Hashida1, Hiroki Miyaoka2, Masanori Hoshino3, Yoichi Koyanagi1, Takuji Yamamoto4, Sanroku Tsukamoto1, Hirotaka Tamura1 Fujitsu Laboratories, Kawasaki, Japan, Fujitsu Semiconductor, Yokohama, Japan
ISSCC 2013
Session 2
Wireline I/O
A 195mW / 55mW Dual-Path Receiver AFE for Multistandard 8.5-to-11.5 Gb/s Serial Links in 40nm CMOS
the deployment of 10Gb/s traffic over legacy data links, such as backplanes (KR) and multimode fiber (MMF) [1]. Under severe channel impairments, an ADC-based receiver with a DSP backend provides robust performance, espe
ISSCC 2013
Session 2
Wireline I/O
A Sub-2W 39.8-to-44.6Gb/s Transmitter and Receiver Chipset with SFI-5.2 Interface in 40nm CMOS
can alleviate bandwidth bottlenecks of Internet infrastructure while simultaneously reducing operating costs. Increasingly, standard CMOS technology is used to enable transceiver speeds [1-5] previously achievable only b
ISSCC 2013
Session 2
Wireline I/O
A 66Gb/s 46mW 3-Tap Decision-Feedback Equalizer in 65nm CMOS
Given the continuously climbing data rates of high-speed I/O’s, equalizer circuits—and particularly decision-feedback equalizer (DFE) designs—are being pushed to operate at ever-higher speeds. At 20 to 40Gb/s data-rates,
ISSCC 2013
Session 2
Wireline I/O
A 32Gb/s Wireline Receiver with a Low-Frequency
Samir Parikh1, Tony Kao1, Yasuo Hidaka1, Jian Jiang1, Asako Toda1, Scott Mcleod1, William Walker1, Yochi Koyanagi2, Toshiyuki Shibuya2, Jun Yamada3 Fujitsu Laboratories of America, Sunnyvale, CA, Fujitsu Laboratories, Ka
ISSCC 2012
Session 24
Wireline I/O
25Gb/s 3.6pJ/b and 15Gb/s 1.37pJ/b VCSEL-Based Optical Links in 90nm CMOS
Future high-performance computing systems require sub-2pJ/bit power efficiencies at >10Gb/s [1-2]. The best reported optical link efficiencies at these data rates are ≥2.5pJ/bit [1-4]. This paper describes two VCSEL-base
ISSCC 2012
Session 24
Wireline I/O
A 10Gb/s Burst-Mode TIA with On-Chip Reset/Lock CM Signaling Detection and Limiting Amplifier with a 75ns Settling Time
France 1 2 Emerging symmetric 10Gb/s passive optical network (PON) systems aim at high network transmission efficiency by reducing the RX settling time that is needed for RX amplitude recovery in burst-mode (BM). A conve
ISSCC 2012
Session 24
Wireline I/O
A 10Gb/s Burst-Mode Laser Diode Driver for Burstby-Burst Power Saving
A burst-mode laser diode driver circuit (BLDD) for 10Gb/s-class passive optical network (10G-EPON) systems reduces power consumption by 94% while the laser diode (LD) is in the off state. The off-state optical launch pow
ISSCC 2012
Session 24
Wireline I/O
A 16-Port FCC-Compliant 10GBASE-T Transmitter and Hybrid with 76dBc SFDR up to 400MHz Scalable to 48 Ports
David Nguyen, Hiok-Tiaq Ng, Ramin Shirani Aquantia, Milpitas, CA High-density 48-port network switches demand very power-efficient, small form-factor quad PHYs which comply with the IEEE 802.3an transmit PSD and return-l
ISSCC 2012
Session 24
Wireline I/O
A Sub-2W 10GBASE-T Analog Front-End in 40nm CMOS process
Ramesh Singh1, Hesam Aslanzadeh1, Alireza Khalili1, Saurabh Vats1, Susan Arno1, Sean Campeau2 Applied Micro, Sunnyvale, CA Applied Micro, Kanata, ON, Canada 1 2 The IEEE802.3an 10GBase-T standard [1] provides full duplex
ISSCC 2011
Session 8
Wireline I/O
A 14Gb/s High-Swing Thin-Oxide Device SST TX in 45nm CMOS SOI
state-of-the-art CMOS technologies makes the design of high-speed transmitters at signaling swings above the typical 1V supply a challenging task. Higher-voltage TX amplitude is not only required in older I/O standards a
ISSCC 2011
Session 8
Wireline I/O
A 1-to-6Gb/s Phase-Interpolator-Based Burst-Mode CDR in 65nm CMOS
are widely used in passive optical networks (PON) [1] and as a replacement for conventional CDRs in clock-forwarding links to reduce power [2]. In PON, a single CDR performs the task of clock and data recovery for severa
ISSCC 2011
Session 8
Wireline I/O
A Highly Digital 0.5-to-4Gb/s 1.9mW/Gb/s SerialLink Transceiver Using Current-Recycling in 90nm CMOS
bandwidth in high performance compute systems is driving the need for energy-efficient multi-Gb/s I/O serial links. Improved power efficiency was demonstrated using adaptive supply regulation [1, 2]. However, power losse
ISSCC 2011
Session 8
Wireline I/O
A 12.5+12.5Gb/s Full-Duplex Plastic Waveguide Interconnect
demand for high-speed, low-cost, and low-overhead I/Os in today’s electronic systems, has been addressed by three general categories of interconnects: electrical, optical, and wireless. The electrical interconnects are t
ISSCC 2011
Session 8
Wireline I/O
10:4 MUX and 4:10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link
Koji Fukuda1, Noboru Masuda1, Ryo Nemoto2, Eiichi Suzuki1, Takashi Takemoto1, Fumio Yuki1, Masayoshi Yagyu1, Hidehiro Toyoda1, Akihiro Kambe1, Tatsuya Saito1, Shinji Nishimura1 1 Hitachi, Tokyo, Japan Hitachi, Ibaraki, J
ISSCC 2011
Session 8
Wireline I/O
A 40Gb/s TX and RX Chip Set in 65nm CMOS
Next generation optical and electrical communications such as chip-to-chip serial links or 100GbE require very-high-speed transceivers. At tens of Gb/s, both transmitters and receivers suffer from inadequate bandwidth an
ISSCC 2011
Session 8
Wireline I/O
A Full-Duplex 10GBase-T Transmitter Hybrid with SFDR >65dBc Over 1 to 400MHz in 40nm CMOS
Teranetics, San Jose, CA A transmitter and echo cancellation hybrid for IEEE 802.3an 10GBase-T Ethernet standard is presented, that utilizes DSP techniques to enhance the linear cancellation, and analog non-linearity can
ISSCC 2011
Session 8
Wireline I/O
Gb/s CMOS SONET-Compliant Transceiver for Both RZ and NRZ Applications
Anand Vasani, Keith Tang, Deyi Pi, Haitao Tong, Siavash Fallahi, Wei Zhang, Ullas Singh, Jun Cao, Bo Zhang, Afshin Momtaz Broadcom, Irvine, CA An 11.3Gb/s CMOS SONET-compliant transceiver is designed to work in both RZ a
ISSCC 2011
Session 25
Wireline I/O
A 13.8mW 3.0Gb/s Clock-Embedded Video Interface with DLL-Based Data-Recovery Circuit
As the panel technology continues to offer displays with higher resolution, greater color depth, and increased frame rate, the amount of video data to display driver ICs (DDIs) inside the panel keeps on expanding. Since
ISSCC 2011
Session 25
Wireline I/O
A 10Gb/s Half-UI IIR-Tap Transmitter in 40nm CMOS
Netlogic Microsystems, Santa Clara, CA Two commercially important standards for 10Gb/s serial data transfer include the SFI specification, associated with SFP+ optical modules and copper twinaxial cable [1], and the 10GB
ISSCC 2011
Session 25
Wireline I/O
A 15Gb/s 0.5mW/Gb/s 2-Tap DFE Receiver with Far-End Crosstalk Cancellation
The increasing demand for high-bandwidth interconnection between integrated circuits requires large numbers of I/Os per chip as well as high data rates per I/O. Key limitations in meeting these requirements include chann
ISSCC 2011
Session 25
Wireline I/O
A 20Gb/s Digitally Adaptive Equalizer/DFE with Blind Sampling
As data rates increase, the backplane communication systems suffer from serious inter-symbol interference (ISI). Due to different channel lengths, loss, and environment variations, an adaptive equalizer is an attractive
ISSCC 2011
Session 25
Wireline I/O
A Digital Wideband CDR with ±15.6kppm Frequency Tracking at 8Gb/s in 40nm CMOS
Seong-Ho Lee1, Hamid Hatamkhani1, Mario Caresosa1, Karo Khanoyan1, Haitao Tong1, Duke Tran1, Anthony Brewster1, Ichiro Fujimori1 1 2 Broadcom, Irvine, CA Broadcom, Austin, TX It has been well understood that the digital
ISSCC 2011
Session 25
Wireline I/O
A TDC-less 7mW 2.5Gb/s Digital CDR with Linear Loop Dynamics and Offset-Free Data Recovery
A clock and data recovery (CDR) circuit is the key building block in all serial communication systems. A classical CDR is implemented using a Type-2 phaselocked loop (PLL) wherein a passive lead-lag analog loop filter is
ISSCC 2011
Session 25
Wireline I/O
A 0.5-to-2.5Gb/s Reference-less Half-Rate Digital CDR with Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance
acquisition range offer flexibility in optical communication networks, help reduce link power through activity-based rate adaptation, and minimize cost with a single-chip multi-standard solution. Extracting the bit rate
ISSCC 2011
Session 25
Wireline I/O
A 5Gb/s Adaptive DFE for 2× Blind ADC-Based CDR in 65nm CMOS (αi, αi+4) are provided to the DFE to be subtracted from the two adjacent samples of ADC, which are ½ UI apart.
For this PD, a triangular waveform is the ideal waveform as its interpolated zerocrossings coincide with the actual zero-crossings. Figure 25.1.3 shows how the amplitude of the desired waveform is generated. Two adjacent
ISSCC 2011
Session 20
Wireline I/O
A 0.076mm2 3.5GHz Spread-Spectrum Clock Generator with Memoryless Newton-Raphson Modulation Profile in 0.13µm CMOS
EMI, which has become a serious problem in high-speed systems. In applications such as serial links, display drivers and consumer electronics, SSCG is essential or strongly recommended. Control options such as frequency