A 0.94mW/Gb/s 22Gb/s 2-Tap Partial-Response DFE Receiver in 40nm LP CMOS

📋 论文概要

该论文提出了一种采用40nm LP CMOS工艺的22Gb/s 2抽头部分响应判决反馈均衡器（prDFE）接收器，通过冗余决策将关键反馈环路从模拟前端移至后切片器域，突破了传统DFE的速度限制，实现了0.94mW/Gb/s的高能效。

💡 主要创新点

• 提出部分响应DFE（prDFE）架构，通过冗余决策将1-UI反馈环路从模拟前端移到数字域，消除了高速设计的瓶颈。
• 在40nm LP CMOS工艺下实现了22Gb/s的数据速率和0.94mW/Gb/s的卓越功耗效率，展示了低功耗高速接收器的设计方法。

🏷 关键词

📄 原文摘要

A decision-feedback equalizer (DFE) reconstructs the post-cursor inter-symbol interference (ISI) pattern from the detected data sequence and subtracts it from the received signal before detecting the next symbol. Therefore, DFE’s operating speed is fundamentally limited by a 1-unit-interval (UI) feedback loop that is often the critical path in high-speed designs. Partial-response DFE (prDFE) architectures push the feedback loop away from the analog front-end to the postslicer domain by making redundant decisions, as shown in Fig. 2.8.1(a). Since distinction between post and current data requires a sequential element to prevent a race, a latch overhead exists in the critical path of many prDFE designs

👥 作者与机构

Kwangmo Jung1, Amir Amirkhany2, Kambiz Kaviani2

University of California, Berkeley, CA, 2Rambus, Sunnyvale, CA