ISSCC 2013
Session 1
Plenary
“Architecting the Future through Heterogeneous Computing”
Advanced Micro Devices, Austin, TX 1. Introduction 1.1 Current Computing Challenges Anyone wishing to drive advances in computing technology must carefully negotiate key trade-offs. First, reducing power consumption is i
ISSCC 2013
Session 1
Plenary
“Smart Life Solutions” from Home to City Yoshiyuki Miyabe
1.0 Introduction If the world continues to consume electric power following current policy, the consumption of power will double by 2035 [1], and by 2030 it is forecast that the human race will need the CO2-absorption ca
ISSCC 2013
Session 1
Plenary
Continuing to Shrink: Next-Generation Lithography - Progress and Prospects Martin van den Brink Executive Vice President and Chief Product & Technology Officer
Optical lithography has been the key manufacturing technology for integratedcircuit production, enabling a million-fold reduction in average transistor length over 50 years. The development of projection scanners, step-a
ISSCC 2013
Session 10
Analog Circuits
A 0.1-to-1.2GHz Tunable 6th-Order N-Path ChannelSelect Filter with 0.6dB Passband Ripple and +7dBm Blocker Tolerance
Radio receivers should be robust to large out-of-band blockers with small degradation in their sensitivity. N-path mixers can be used as mixer-first receivers [1] with good linearity and RF filtering [2]. However, 1/f no
ISSCC 2013
Session 10
Analog Circuits
A 2mW 800MS/s 7th-Order Discrete-Time IIR Filter with 400kHz-to-30MHz BW and 100dB Stop-Band Rejection in 65nm CMOS
Filters are key building blocks in wireless communication and analog signal processing. Typically, Gm-C and active-RC topologies are being used for this purpose. However, reduced supply voltage and lower transistor outpu
ISSCC 2013
Session 10
Analog Circuits
A Multi-Path Chopper-Stabilized Capacitively Coupled Operational Amplifier with 20V-InputCommon-Mode Range and 3μV Offset
Capacitively coupled chopper amplifiers are capable of handling common-mode voltages outside their supply rails, while also achieving high power efficiency and low offset [1-3]. However, a significant drawback of such am
ISSCC 2013
Session 10
Analog Circuits
A 0.06mm2 14nV/√Hz Chopper Instrumentation Amplifier with Automatic Differential-Pair Matching
Electronics-Inspired Interdisciplinary Research Institute (EIIRIS), Toyohashi, Japan 1 2 A small-area low-power low-noise instrumentation amplifier (IA) is desired in arrayed sensor devices that are used for high-spatial
ISSCC 2013
Session 10
Analog Circuits
A 4Ω 2.3W Class-D Audio Amplifier with Embedded
higher audio output power. This can be achieved by lowering the speaker impedance or increasing the voltage swing at the amplifier output by boosting the supply voltage [1-4]. Typical speakers in portable devices are qui
ISSCC 2013
Session 10
Analog Circuits
A 62mW Stereo Class-G Headphone Driver with 108dB Dynamic Range and 600μA/Channel Quiescent Current
A differential to singleended block (D2S) converts the output voltage of the Gm-C loop filter into an appropriate single-ended signal at the input of the class-AB and class-B amplifiers. The architecture suppresses error
ISSCC 2013
Session 10
Analog Circuits
A 120nW 18.5kHz RC Oscillator with Comparator Offset Cancellation for ±0.25% Temperature Stability
Anantha P. Chandrakasan1, Gangadhar Burra2 Massachusetts Institute of Technology, Cambridge, MA, Texas Instruments, Dallas, TX, 3MediaTek, Austin, TX 1 2 Integrated low-frequency oscillators can replace crystal oscillato
ISSCC 2013
Session 10
Analog Circuits
A 0.45V 423nW 3.2MHz Multiplying DLL with Leakage-Based Oscillator for Ultra-Low-Power Sensor Platforms
University of Michigan, Ann Arbor, MI 1 2 Emerging demands on ultra-low-power wireless sensor platform have presented challenges for nano-watt design of various circuit components. Clock management unit, as an essential
ISSCC 2013
Session 11
Memory
A 3.4pJ FeRAM-Enabled D Flip-Flop in 0.13µm CMOS for Nonvolatile Processing in Digital Systems
Texas Instruments, Dallas, TX 1 2 Nonvolatile processing—continuously operating a digital circuit and retaining state through frequent power interruptions—creates new applications for portable electronics operating from
ISSCC 2013
Session 11
Memory
Nonvolatile Logic-in-Memory Array Processor in 90nm MTJ/MOS Achieving 75% Leakage Reduction Using Cycle-Based Power Gating
Ryusuke Nebashi2, Yukihide Tsuji2, Ayuka Morioka2, Tadahiko Sugibayashi2, Sadahiko Miura2, Hiroaki Honjo2, Keizo Kinoshita1, Shoji Ikeda1, Tetsuo Endoh1, Hideo Ohno1, Takahiro Hanyu1 Tohoku University, Sendai, Japan, 2 N
ISSCC 2013
Session 11
Memory
A Versatile Timing Microsystem Based on WaferLevel Packaged XTAL/BAW Resonators with Sub-µW RTC Mode and Programmable HF Clocks
Silvio Dalla Piazza2, Felix Staub2, Kai Zoschke3, Charles Alix Manier3, Hermann Oppermann3, James Dekker4, Tommi Suni4, Giorgio Allegato5 CSEM, Neuchatel, Switzerland, Micro Crystal, Grenchen, Switzerland, 3Fraunhofer IZ
ISSCC 2013
Session 11
Memory
Microwave Amplification with Nanomechanical Resonators
beam resonators. One such mechanical device is illustrated in Fig. 11.4.7. The fabrication relies on e-beam patterning, gas phase HF-etching, and release of the Al-beam using focused ion beam (FIB) cutting, as described
ISSCC 2013
Session 11
Memory
A 0.15mm-Thick Non-Contact Connector for MIPI Using Vertical Directional Coupler
capabilities should also be improved to achieve higher overall system performance. This paper proposes a new, small-size and high-speed non-contact interconnect between printed circuit boards (PCBs) using a vertical dire
ISSCC 2013
Session 11
Memory
Gb/s 3.9pJ/b Mono-Phase Pulse-Modulation Inductive-Coupling Transceiver for mm-Range Board-to-Board Communication
relaxing hardware requirements and leading to low energy consumption in the transceiver. Figure 11.6.4 shows the spectrum waveform of the receiver output. The 1.09GHz free running frequency is locked to the 1.2GHz clock
ISSCC 2013
Session 11
Memory
Retrodirective Transponder Array with Universal On-Sheet Reference for Wireless Mobile Sensor Networks Without Battery or Oscillator
A rotating shaft in a wheel, a motor and a turbine uses sensors to measure torque, vibration, and acceleration for better control and maintenance of a machine. Such data is currently acquired in a laboratory and utilized
ISSCC 2013
Session 11
Memory
A Scalable 2.9mW 1Mb/s eTextiles Body Area Network Transceiver with Remotely Powered Sensors and Bi-Directional Data Communication
Masdar Institute of Science and Technology, Abu Dhabi, United Arab Emirates 1 2 Advances in sensor design have made ambulatory health monitoring possible and have created the need for low-power communication systems to r
ISSCC 2013
Session 12
Memory
A 130.7mm2 2-Layer 32Gb ReRAM Memory Device in 24nm Technology
Jeffrey KoonYee Lee1, Gopinath Balakrishnan1, Gordon Yee1, Henry Zhang1, Alex Yap1, Jingwen Ouyang1, Takahiko Sasaki2, Sravanti Addepalli1, Ali Al-Shamma1, Chin-Yu Chen1, Mayank Gupta1, Greg Hilton1, Saurabh Joshi1, Acha
ISSCC 2013
Session 12
Memory
40nm Embedded SG-MONOS Flash Macros for Automotive with 160MHz Random Access for Code and Endurance Over 10M Cycles for Data
markets of Flash MCUs, microcontrollers with embedded flash memory (eFlash), have been steadily growing since the middle of 1990s. Especially, in automotive, Flash MCUs have become essential to realize the complicated re
ISSCC 2013
Session 12
Memory
A 6nW Inductive-Coupling Wake-Up Transceiver for Reducing Standby Power of Non-Contact Memory Card by 500×
Memory cards are widely used in electronic systems to expand internal storage area or are used as detachable media to carry data. Although cloud computing has recently drawn attention, data transfer consumes significant
ISSCC 2013
Session 12
Memory
Time-Differential Sense Amplifier for Sub-80mV Bitline Voltage Embedded STT-MRAM in 40nm CMOS
Jan Otterstedt1, Othmane Bahlous1, Karl Hofmann1, Robert Allinger1, Stephan Kassenetter1, Doris Schmitt-Landsiedel2 Infineon Technologies, Neubiberg, Germany, Technical University Munich, Munich, Germany 1 2 Spin-torque-
ISSCC 2013
Session 12
Memory
A 128Gb 3b/cell NAND Flash Design Using 20nm Planar-Cell Technology
P. Conenna1, A. D’Alessandro1, L. De Santis1, D. Di Cicco1, W. Di Francesco1, M.L. Gallese1, G. Gallo2, M. Incarnati1, C. Lattaro1, A. Macerola1, G. Marotta1, V. Moschiano1, D. Orlandi1, F. Paolini1, S. Perugini1, L. Pil
ISSCC 2013
Session 12
Memory
Filament Scaling Forming Technique and Level-Verify-Write Scheme with Endurance Over 107 Cycles in ReRAM
Ryotaro Azuma1, Yuhei Yoshimoto1, Kouhei Tanabe2, Zhiqiang Wei1, Takeki Ninomiya1, Koji Katayama1, Ryutaro Yasuhara1, Shunsaku Muraoka1, Atsushi Himeno1, Naoki Yoshikawa1, Hideaki Murase1, Kazuhiko Shimakawa1, Takeshi Ta
ISSCC 2013
Session 12
Memory
A 45nm 6b/cell Charge-Trapping Flash Memory Using LDPC-Based ECC and Drift-Immune Soft-Sensing Engine
multiple-bits-per-cell technique is widely adopted. As presented in [1], a 4b/cell Flash memory by using error-detection (ED) scheme stores 2b data on two sides of a memory cell individually. Since the noise margin becom
ISSCC 2013
Session 12
Memory
Cycling Endurance Optimization Scheme for 1Mb STT-MRAM in 40nm Technology
Yu-Der Chih, Tong-Chern Ong, Jonathan Chang, Sreedhar Natarajan, Luan C. Tran TSMC, Hsinchu, Taiwan Spin-transfer-torque (STT) MRAM is considered as a good candidate for nextgeneration memory that can replace Flash, SRAM
ISSCC 2013
Session 12
Memory
Unified Solid-State-Storage Architecture with NAND Flash Memory and ReRAM that Tolerates 32× Higher BER for Big-Data Applications
Unified solid-state storage (USSS) provides high error tolerance with four techniques: reverse-mirroring (RM), error-reduction synthesis (ERS), page-RAID, and error-masking (EM). The acceptable raw bit-error rate (ABER)
ISSCC 2013
Session 13
Wireless
A Fully Integrated 60GHz CMOS Transceiver Chipset Based on WiGig/IEEE802.11ad with Built-In Self Calibration for Mobile Applications
Koichiro Tanaka, Junji Sato, Yohei Morishita, Masaki Kanemaru, Ryo Kitamura, Takahiro Shima, Toshifumi Nakatani, Kenji Miyanaga, Tomoya Urushihara, Hiroyuki Yoshikawa, Takenori Sakamoto, Hiroyuki Motozuka, Yoshinori Shir
ISSCC 2013
Session 13
Wireless
A Digitally Modulated mm-Wave Cartesian Beamforming Transmitter with Quadrature Spatial Combining
With fast-growing demand for high-speed mobile communications and highly saturated spectral usage below 10GHz, mm-Wave frequency bands are emerging as the key playground for future high-data-rate wireless standards. Rece
ISSCC 2013
Session 13
Wireless
A 50mW-TX 65mW-RX 60GHz 4-Element Phased-Array Transceiver with Integrated Antennas in 65nm CMOS
The 60GHz band has gained great interest as an enabler for multi-Gb/s wireless links. Recent efforts [1-4] have focused on reducing transceiver power to drive adoption of 60GHz in mobile devices. To further accelerate th
ISSCC 2013
Session 13
Wireless
A Low-Power Radio Chipset in 40nm LP CMOS with Beamforming for 60GHz High-Data-Rate Wireless Communication
Giovanni Mangraviti1,2, Steven Brebels1, Wim van Thillo1, Kristof Vaesen1, Bertrand Parvais1, Vadim Issakov1, Mike Libois1, Michiaki Matsuo3, John Long4, Charlotte Soens1, Piet Wambacq1,2 imec, Leuven, Belgium, 2Vrije Un
ISSCC 2013
Session 13
Wireless
A Mixed-Signal 32-Coefficient RX-FFE 100Coefficient DFE for an 8Gb/s 60GHz Receiver in 65nm LP CMOS
The 60GHz band has opened the opportunity for multi-Gb/s wireless communications, and is being commercially supported by transceiver solutions utilizing the WirelessHD and/or WiGig standards. However, the hundreds of mWs
ISSCC 2013
Session 13
Wireless
A 2-to-16GHz 204mW 3mm-Resolution SteppedFrequency Radar for Breast-Cancer Diagnostic Imaging in 65nm CMOS
Radar imaging is gaining interest for medical, security, and industrial applications. Enabled by the advances in silicon technologies, a clear trend towards higher integration is observed [1-3]. Early-stage breast cancer
ISSCC 2013
Session 13
Wireless
A Scalable Direct-Sampling Broadband Radar Receiver Supporting Simultaneous Digital Multibeam Array in 65nm CMOS
Intelligent environments significantly impact human daily lives through embedded sensing and actuating systems. Wireless sensors that can provide non-contact radio information are indispensable. Impulse radar is position
ISSCC 2013
Session 13
Wireless
A Digital Single-Wire Multiswitch (DSWM) ChannelStacking IC in 45nm CMOS for Satellite Outdoor Units
Costantino Pala1, Jiang Cao1, Jaspreet Bhatia1, Mikko Waltari1, Lior Levin1, Cyrille Cathelin2, Thierry Nouvet2, Nitin Nidhi1, Rahul Kodkani1, Ryuji Maeda1, Damian Costa1, Jason McFee1, Reza Moazzam1, Herve Vincent2, Phi
ISSCC 2013
Session 14
Digital Circuits
A 0.022mm2 970μW Dual-Loop Injection-Locked PLL with -243dB FOM Using Synthesizable All-Digital PVT Calibration Circuits
include low area, low power consumption, environmental insensitivity, and the lowest possible jitter performance. Multiplying Delay-Locked Loop (MDLL) [12], subharmonically injection-locked techniques [3], and sub-sampli
ISSCC 2013
Session 14
Digital Circuits
A 0.032mm2 3.1mW Synthesized Pixel Clock Generator with 30psrms Integrated Jitter and 10-to-630MHz DCO Tuning Range
digital TVs and also in other video applications. A low integrated jitter is required for good display quality. However, an extremely low input frequency coming from the horizontal synchronization signal (HSYNC) makes it
ISSCC 2013
Session 14
Digital Circuits
An All-Digital PLL Using Random Modulation for SSC Generation in 65nm CMOS
This paper introduces a digital PLL which uses high-frequency random modulation (RM), as opposed to low-frequency periodic modulation, to generate a spread spectrum clock (SSC). The implementation is straightforward and
ISSCC 2013
Session 14
Digital Circuits
A 0.026mm2 5.3mW 32-to-2000MHz Digital Fractional-N Phase Locked-Loop Using a Phase-Interpolating Phase-to-Digital Converter
from analog circuits to their digital counterparts, with digital PLLs (DPLLs) being an example of this trend [1]. All-digital or fully synthesizable approaches, which exploit the merits of advanced processes, suffer from
ISSCC 2013
Session 14
Digital Circuits
A 2.5GHz 2.2mW/25μW On/Off-State Power 2psrmsLong-Term-Jitter Digital Clock Multiplier with 3-Reference-Cycles Power-On Time
dissipation and increase battery life. By turning off the circuits that are not in use, power cycling provides a viable means to make power dissipation proportional to workload, hence achieving energy proportional operat
ISSCC 2013
Session 14
Digital Circuits
3D Clock Distribution Using Vertically/HorizontallyCoupled Resonators
Clock distribution with low skew, low jitter, and low power for high-performance microprocessors is a significant design challenge. Although traditional H-tree clock distribution circuits are widely used, the clock skew
ISSCC 2013
Session 14
Digital Circuits
All-Digital Hybrid Temperature Sensor Network for Dense Thermal Monitoring
spatial temperature distribution, which is essential for dynamic thermal management [1,2]. The number of on-chip temperature sensors in highperformance processors is increasing, with state-of-the-art commercial processor
ISSCC 2013
Session 14
Digital Circuits
A 95fJ/b Current-Mode Transceiver for 10mm On-Chip Interconnect
sense-amplifier load in the receiver. In this work, IDRV and IPE were set to 95μA and 45μA, respectively. For the receiver equalization, the PMOS diode in the sense-amplifier load is modified to form an active inductor c
ISSCC 2013
Session 14
Digital Circuits
Razor-Lite: A Side-Channel Error-Detection Register for Timing-Margin Recovery in 45nm SOI CMOS
University of Michigan, Ann Arbor, MI Advanced CMOS technologies are highly susceptible to process, voltage, and temperature (PVT) variations due to sub-wavelength lithography and other manufacturing challenges. These va
ISSCC 2013
Session 15
Data Converters
A 28fJ/conv-step CT ΔΣ Modulator with 78dB DR and 18MHz BW in 28nm CMOS Using a Highly Digital Multibit Quantizer
compensation and high-order single-opamp integrators have achieved FoM values well below 100fJ/conv-step [1-3]. With loop-filter power greatly reduced, power dissipation in multibit quantizers becomes especially signific
ISSCC 2013
Session 15
Data Converters
A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with Data-Driven Noise Reduction
Low-power sensor applications e.g. for environmental monitoring, bio-potential recording, and wireless autonomous sensor networks require highly power-efficient ADCs, typically with resolutions of at least 10b. SAR ADCs
ISSCC 2013
Session 15
Data Converters
A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR Enhancement Techniques Utilizing Noise
utilizes the high switching speed of nanometer CMOS processes. In recent reports, time-interleaving techniques and multi-bit-per-cycle conversion have boosted speed to the GHz sampling range at low power consumption. How
ISSCC 2013
Session 15
Data Converters
A 1V 14b Self-Timed Zero-Crossing-Based Incremental ΔΣ ADC
This paper introduces a clock-free self-timed incremental ΔΣ ADC. Unlike conventional ΔΣ ADCs, it does not require a dedicated clock signal, thus saving energy and reducing system complexity. As such, it has similar adva
ISSCC 2013
Session 15
Data Converters
A 6.3μW 20b Incremental Zoom-ADC with 6ppm INL and 1μV Offset
Delft University of Technology, Delft, The Netherlands 1 2 Incremental analog-to-digital converters (ADCs) can be applied in many instrumentation applications, such as the readout of bridge transducers and smart sensors
第 1/5 页 · 共 210 篇 · 下一页 →