A 65nm 39GOPS/W 24-Core Processor with 11Tb/s/W Packet-Controlled Circuit-Switched Double-Layer Network-on-Chip and Heterogeneous Execution Array

📋 论文概要

该论文设计了一款65nm工艺的24核处理器，用于多媒体和通信应用，核心特点是采用包控电路交换双层片上网络（NoC），实现了11Tb/s/W的能效和435Gb/s的二分带宽。通过簇共享NoC连接异构可重构加速器，在满足高灵活性的同时提升了性能和能效。

💡 主要创新点

• 提出包控电路交换双层NoC架构，结合电路交换和包交换优势，实现高能效（11Tb/s/W）和高带宽（435Gb/s二分带宽）。
• 采用簇共享NoC连接的异构可重构架构，将通用处理器核与专用加速器集成，兼顾灵活性与计算效率。
• 在65nm工艺下实现39GOPS/W的整体能效，适合计算密集型多媒体和通信应用。

🏷 关键词

📄 原文摘要

programmable multicore processors are drawing attention due to their high flexibility and low implementation cost, yet their performance and energy efficiency still cannot fulfill the demands of many compute-intensive applications. This paper describes a high-performance energy-efficient 24-core processor for multi-media and communication applications, with the following key features: (1) a packet-controlled circuit-switched double-layer network-on-chip (NoC) which provides 11Tb/s/W energy efficiency with 435Gb/s bisection-bandwidth; (2) a cluster-shared NoCconnected heterogeneous reconfigurable execution array, which can improve the performance of frequently used computations in multimedia and communication

👥 作者与机构

Peng Ou, Jiajie Zhang, Heng Quan, Yi Li, Maofei He, Zheng Yu,

Xueqiu Yu, Shile Cui, Jie Feng, Shikai Zhu, Jie Lin, Ming’e Jing, Xiaoyang Zeng, Zhiyi Yu Fudan University, Shanghai, China With the increasing complexity and variety of applications,