⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种低功耗（3.1mW）的相位可调正交时钟生成方法，无需频率转换即可从两相时钟产生正交相位，适用于CEI 28G短距离CDR。解决了传统分频器或耦合LC-VCO方法在25Gb/s以上多通道实现中功耗和面积大的问题。
phases at low area and power overhead from a two-phase clock without frequency conversion is desirable for half-rate CDR architectures. This is useful for both embedded and forwarded clock systems, where quadrature generation by dividers, ring oscillators or coupled LC-VCOs is common. For example, [1] uses LC-VCOs followed by 2:1 dividers to generate the half-rate clocks for both TX and RX in a 28Gb/s transceiver. However, such an approach tends to be power- and area-inefficient for multi-lane implementations at data rates of 25Gb/s and beyond. We present a quadrature generation method that uses two 30×30μm2 0.85nH inductors and consumes 3.1mW at 13.5GHz, excluding buffering, while generating quadrature phases at the same frequency with an accuracy of 1.5°. The method generates quadrature signals by adding 20% to the power consumed by
Kanupriya Bhardwaj1, Sriram Narayan2, Sergey Shumarayev3, Thomas Lee1
Stanford University, Stanford, CA, Inphi, Santa Clara, CA, 3 Altera, San Jose, CA 1 2 Generating quadrature