A 56.4-to-63.4GHz Spurious-Free All-Digital Fractional-N PLL in 65nm CMOS

📋 论文概要

该论文提出了一种基于60GHz全数字分数-N锁相环（ADPLL）的毫米波数字发射机，解决了60GHz下MOS变容管Q值低导致DCO性能差的问题。通过两点调频实现宽带调制，并支持高度可重构性，适用于低成本、高集成度的射频与基带电路集成。

💡 主要创新点

• 提出了一种60GHz全数字分数-N锁相环架构，克服了毫米波频段DCO品质因数低的挑战。
• 采用两点调频（two-point FM）技术，实现了宽带频率调制，支持高数据率传输。
• 设计了高度可重构的发射机架构，提升了射频与基带电路的集成度，降低了成本。

🏷 关键词

📄 原文摘要

University of Science and Technology of China, Hefei, China 1 2 Frequency synthesis at mm-Waves is still dominated by analog PLLs, although all-digital PLLs (ADPLLs) [1] have been widely explored below 10GHz. The major obstacle has been the poor quality of digitally controlled oscillators (DCO) as MOS varactor Q-factor drops to <10 at 60GHz. A mm-Wave digital transmitter (TX) based on a 60GHz fractional-N ADPLL with two-point FM is proposed here. The TX features extensive reconfigurability and permits the highest degree of integration of RF and baseband circuitry for low-cost, high-volume applications. To simplify the TX architecture, the synthesizer is capable of FM, hence a timeto-digital converter (TDC) is preferred over bang-bang phase detection. With the aid of autonomous calibrations of DCO and TDC gain, wideband two-point FM is achieved. Figure 20.4.1 shows a diagram of the 60GHz ADPLL with a DCO oscillating

👥 作者与机构

Wanghua Wu1, Xuefei Bai1,2, Robert Bogdan Staszewski1, John R. Long1

Delft University of Technology, Delft, The Netherlands,