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本文开发了基于20nm完全平面单元工艺的128Gb 3b/cell NAND闪存，解决了高密度存储下的可靠性和性能挑战。该设计实现了在先进工艺节点下每单元存储3位的超高密度，为低成本大容量存储提供了解决方案。
P. Conenna1, A. D’Alessandro1, L. De Santis1, D. Di Cicco1, W. Di Francesco1, M.L. Gallese1, G. Gallo2, M. Incarnati1, C. Lattaro1, A. Macerola1, G. Marotta1, V. Moschiano1, D. Orlandi1, F. Paolini1, S. Perugini1, L. Pilolli1, P. Pistilli2, G. Rizzo2, F. Rori1, M. Rossini1, G. Santin1, E. Sirizotti1, A. Smaniotto2, U. Siciliani2, M. Tiburzi1, R. Meyer3, A. Goda3, B. Filipiak3, T. Vali1, M. Helm4, R. Ghodsi4 Micron, Avezzano, Italy, Micron, Padua, Italy, 3 Micron, Boise, ID, 4Micron, San Jose, CA 1 2 We develop a 128Gb 3b/cell NAND Flash memory based on 20nm fully planar cell process technology. The planar cell allows the memory cell to be scaled in both the wordline (WL) and bitline (BL) directions, resulting in a small 3b/cell memory device. The sensing scheme is based on a ramping technique that allows the detection of hard and soft states in a single operation. The data cache structure is designed to efficiently manage features that optimize
G. Naso1, L. Botticchio1, M. Castelli1, C. Cerafogli1, M. Cichocki1,