A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS

📋 论文概要

本文提出一种采用交替比较器的异步冗余单通道SAR ADC，在32nm数字SOI工艺下实现1.2GS/s采样率，功耗仅3.1mW，解决了高速与低功耗的权衡问题。

💡 主要创新点

• 提出交替比较器结构，通过两个比较器交替工作来提升异步SAR ADC的转换速度，减少比较器复位时间的影响。
• 采用异步冗余转换方案，结合冗余电容DAC，允许更快的逐次逼近过程，同时保持8位精度。

🏷 关键词

📄 原文摘要

Christian Menolfi1, Matthias Braendli1, Marcel Kossel1, Thomas Morf1, Toke Meyer Andersen1, Yusuf Leblebici2 IBM Research, Rüschlikon, Switzerland, 2EPFL, Lausanne, Switzerland 1 Next-generation digital high-speed links require fast, yet energy-efficient ADCs at minimum area. Recent years saw impressive progress in SAR ADC designs towards higher sampling speed. Asynchronous clocking [2-5], redundant capacitive DACs (CDAC) [2], multi-bit decisions per step [1,3-4] and interleaved designs [2-3] have been presented. We present an asynchronous redundant single-channel ADC achieving 1.2GS/s at 1V supply by using two comparators in alternation to relax comparator reset timing. The ADC achieves 39.3dB SNDR and 34fJ/conversion-step with a core chip area of 0.0015mm2. Figure 26.4.1 shows a block diagram of the ADC. The front-end T&H circuit consists of a sampling switch with feed-through and charge-injection compensation. The external clock ckext running at 12.5% duty cycle drives the T&H circu

👥 作者与机构

Lukas Kull1,2, Thomas Toifl1, Martin Schmatz1, Pier Andrea Francese1,