An 8MHz 75μA/MHz Zero-Leakage Non-Volatile Logic-Based Cortex-M0 MCU SoC Exhibiting 100% Digital State Retention at VDD=0V with <400ns Wakeup and Sleep Transitions

📋 论文概要

本文提出一种基于非易失性逻辑（NVL）的Cortex-M0 MCU SoC，能够在电源中断时自动备份所有触发器状态，实现100%数字状态保留。该SoC在休眠模式下零泄漏，恢复时间小于400ns，功耗为75μA/MHz，工作频率8MHz，解决了能量采集应用中高待机功耗或重启开销的问题。

💡 主要创新点

• 提出基于非易失性逻辑的SoC架构，在电源中断时自动备份所有数字状态，无需额外电源维持。
• 实现零泄漏休眠模式，系统状态可在400ns内恢复，显著降低待机功耗，适用于能量采集场景。

🏷 关键词

📄 原文摘要

Scott R. Summerfelt, John A. Rodriguez, Hugh P. McAdams Texas Instruments, Dallas, TX We demonstrate a non-volatile logic (NVL)-based SoC that backs up its working state (all flip-flops) upon receiving a power interrupt, has zero leakage in sleep mode, and needs less than 400ns to restore the system state upon power-up. Without NVL, a chip would either have to keep all flip-flops powered resulting in high standby power, or waste energy and time rebooting after power-up. For energy harvesting applications, NVL is a “must have” because there is no constant power source available to keep flip-flops (FFs) alive, and even when the intermittent power source is available, boot-up code alone may consume all of the harvested energy. For handheld devices with limited cooling and battery capacity, zero-leakage IC’s with “instant-on” capability are ideal. Our SoC features a Cortex-M0 core, UART and SPI interfaces, and 10KB ROM,

👥 作者与机构

Steven C. Bartling, Sudhanshu Khanna, Michael P. Clinton,