A 2mW 800MS/s 7th-Order Discrete-Time IIR Filter with 400kHz-to-30MHz BW and 100dB Stop-Band Rejection in 65nm CMOS

📋 论文概要

该论文提出了一种基于离散时间（DT）模拟信号处理方法的7阶IIR低通滤波器，在65nm CMOS工艺中实现了2mW功耗、800MS/s采样率、400kHz至30MHz可调带宽和100dB阻带抑制，解决了传统Gm-C和active-RC滤波器在低电压下难以实现高增益宽带宽且功耗效率低的问题。

💡 主要创新点

• 采用离散时间模拟信号处理架构，避免了高性能运算放大器的需求，降低了功耗并提高了可调性。
• 实现了7阶IIR滤波器的高阶阻带抑制（100dB）与宽带宽可调范围（400kHz-30MHz），同时保持极低功耗（2mW）。

🏷 关键词

📄 原文摘要

Filters are key building blocks in wireless communication and analog signal processing. Typically, Gm-C and active-RC topologies are being used for this purpose. However, reduced supply voltage and lower transistor output impedance make it difficult to implement high-gain wide-bandwidth opamps in a power-efficient manner. Moreover, portable wireless communication devices demand nowadays ever decreasing power consumption, and more tunability/reprogrammability. A discrete-time (DT) analog signal processing approach appears to answer these requirements. A simple first-order DT IIR low-pass filter is depicted in Fig. 10.2.1 (top-left) [1]. A gm-stage converts the input voltage to current. In each cycle, history capacitor (CH) integrates this current and stores the charge. This charge is shared with a sampling capacitor (CS) in ϕ1. In ϕ2, the charge stored in CS is reset to zero. In this filter, the ratio of CS/CH and sampling frequency determine the bandwidth

👥 作者与机构

Massoud Tohidian, Iman Madadi, Robert Bogdan Staszewski

Delft University of Technology, Delft, The Netherlands