Nonvolatile Logic-in-Memory Array Processor in 90nm MTJ/MOS Achieving 75% Leakage Reduction Using Cycle-Based Power Gating

📋 论文概要

该论文提出了一种基于MTJ/MOS混合技术的非易失性逻辑-内存（NV-LIM）阵列处理器，通过循环电源门控技术实现了75%的漏电减少，解决了传统CMOS VLSI处理器的功耗瓶颈问题。

💡 主要创新点

• 采用MTJ器件分布集成在CMOS逻辑电路平面上的非易失性逻辑-内存架构，实现常态关断与即时启动功能。
• 提出基于周期的电源门控（Cycle-Based Power Gating）技术，显著降低静态漏电功耗。
• 在90nm工艺节点验证了MTJ/MOS混合集成处理器的可行性，实现了超过75%的漏电降低。

🏷 关键词

📄 原文摘要

Ryusuke Nebashi2, Yukihide Tsuji2, Ayuka Morioka2, Tadahiko Sugibayashi2, Sadahiko Miura2, Hiroaki Honjo2, Keizo Kinoshita1, Shoji Ikeda1, Tetsuo Endoh1, Hideo Ohno1, Takahiro Hanyu1 Tohoku University, Sendai, Japan, 2 NEC, Tsukuba, Japan 1 Nonvolatile logic-in-memory (NV-LIM) architecture [1], where magnetic tunnel junction (MTJ) devices [2] are distributed over a CMOS logic-circuit plane, has the potential of overcoming the serious power-consumption problem that has rapidly become a dominant constraint on the performance improvement of today’s VLSI processors. Normally-off and instant-on capabilities with a small area penalty due to non-volatility and three-dimensional-stackability of MTJ devices in the above structure allow us to apply a power-gating technique in a fine temporal granularity, which can perfectly eliminate wasted power dissipation due to leakage current. The impact of embedding nonvolatile memory

👥 作者与机构

Masanori Natsui1, Daisuke Suzuki1, Noboru Sakimura2,