A Low-Power 1GHz Razor FIR Accelerator with Time-Borrow Tracking Pipeline and Approximate Error Correction in 65nm CMOS

📋 论文概要

本文提出了一款基于Razor技术的低功耗1GHz FIR加速器，采用时间借用跟踪流水线和近似纠错电路，在65nm CMOS工艺中实现。通过消除静态电压裕度，显著降低了功耗，并提供了对延迟故障的弹性。

💡 主要创新点

• 首次将Razor技术应用于DSP加速器（FIR）而非传统微处理器流水线，拓展了Razor的应用范围。
• 提出时间借用跟踪流水线结构，有效处理时序违规并提高吞吐量。
• 采用近似纠错机制，在允许少量误差的情况下进一步降低功耗。

🏷 关键词

📄 原文摘要

ARM, Cambridge, United Kingdom The unrelenting demands of wireless/multimedia DSP workloads necessitate specialized hardware to achieve higher performance and power efficiency. Razor systems offer even greater power efficiency by minimizing static supply voltage (VDD) guardbands for process/voltage/temperature (PVT) variation, while also providing a degree of resilience to general delay faults (e.g. SEUs). To date, Razor has only been demonstrated on silicon in the context of microprocessor pipelines [1][2]. Reported Algorithmic Noise Tolerance (ANT) circuits [3][4] operate at very high error rates, but rely on imbalanced ripple-carry adders and hence clock frequency (Fclk) is limited (50–88MHz). ANT also requires additional datapaths for error detection/correction, which cannot be clock gated in the absence of errors, increasing baseline area and power. Combining Razor error detection with algorithm-level correction enables high-Fclk datapaths and lowoverheads. A 0.19mm2 16-tap Razor

👥 作者与机构

Paul N. Whatmough, Shidhartha Das, David M. Bull