A 195mW / 55mW Dual-Path Receiver AFE for Multistandard 8.5-to-11.5 Gb/s Serial Links in 40nm CMOS

📋 论文概要

本文提出了一种用于多标准8.5-11.5 Gb/s串行链路的双路径接收器模拟前端，通过ADC-DSP路径和二进制切片路径的并行架构，在严重信道损伤下提供鲁棒性能，同时针对低损耗信道实现低功耗。

💡 主要创新点

• 提出双路径接收器架构，结合ADC-DSP路径和二进制切片路径，根据信道条件动态选择最优路径，兼顾高性能与低功耗。
• 在40nm CMOS工艺中实现195mW（ADC路径）和55mW（二进制路径）的功耗，支持8.5-11.5 Gb/s多标准速率。

🏷 关键词

📄 原文摘要

the deployment of 10Gb/s traffic over legacy data links, such as backplanes (KR) and multimode fiber (MMF) [1]. Under severe channel impairments, an ADC-based receiver with a DSP backend provides robust performance, especially for MMF applications, due to the complexity of the channel pulse response and the dynamic nature of the channel impairment. The reach of the backplane channels can also be extended, providing flexibility for system design. Applications such as 10G SFP+ DAC have less channel loss; consequently, a slicer-based binary receiver is a more viable low-power solution. This work describes the AFE of a dual-path receiver that uses both an ADC path and a slicer path for 10Gb/s multistandard applications in 40nm CMOS. The block diagram of the dual-path receiver is shown in Fig. 2.4.1. In the ADC

👥 作者与机构

Bo Zhang, Ali Nazemi, Adesh Garg, Namik Kocaman,

Mahmoud Reza Ahmadi, Mehdi Khanpour, Heng Zhang, Jun Cao, Afshin Momtaz Broadcom, Irvine, CA Demand for bandwidth in metro networks and data centers has fueled