An 11b 3.6GS/s Time-Interleaved SAR ADC in 65nm CMOS

📋 论文概要

本文提出了一种11位3.6GS/s的时间交错SAR ADC，采用65nm CMOS工艺，旨在提高采样率以满足雷达、软件无线电等应用需求。通过时间交错架构实现了高速低功耗采样。

💡 主要创新点

• 实现了3.6GS/s的高采样率，相较于之前2.5-3.0GS/s的同类设计有显著提升。
• 采用65nm CMOS工艺，在保持低功耗的同时达到11位分辨率。

🏷 关键词

📄 原文摘要

Alessandro Murroni1, Gerard van der Weide1, Yu Lin1, Ludo Alvado2, Frederic Darthenay2, Yannick Fregeais2 NXP Semiconductors, Eindhoven, The Netherlands, NXP Semiconductors, Caen, France 1 2 Over the last years several low-power time-interleaved (TI) ADC designs in the 2.5-to-3.0GS/s range have been published [1-3], intended for integration in applications like radar, software-defined radio, full-spectrum cable modems, and multi-channel satellite reception. It is to be expected that future generations of these applications will require a higher ADC sampling rate, while maintaining good high-frequency linearity. Furthermore, a high spectral purity is desired, as spurs can cause an SNR degradation of several dB for weak narrowband signals. For interleaved converters, this mandates an output with limited interleaving artifacts. For the reception of broadband and multi-carrier signals, the gain mismatch and time-skew tones do not typically limit performance, since the spurs

👥 作者与机构

Erwin Janssen1, Kostas Doris1, Athon Zanikopoulos1,