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本文介绍了一款在28nm UTBB FDSOI工艺上实现的IEEE 802.11n LDPC解码器，展示了该电路相比28nm LP高k金属栅CMOS体硅工艺的性能优势，并引入了扩展体偏置范围技术以提升能效。
Bertrand Pelloux-Prayer1, Fabien Giner1, Deepak-Kumar Arora3, Franck Arnaud1, Nicolas Planes1, Julien Le Coz1, Olivier Thomas2, Sylvain Engels1, Giorgio Cesana1, Robin Wilson1, Pascal Urard1 STMicroelectronics, Crolles, France, 2CEA-LETI-MINATEC, Grenoble, France, STMicroelectronics, Greater Noida, India 1 3 This paper presents an IEEE 802.11n Low-Density Parity-Check (LDPC) decoder implemented in 28nm Ultra-Thin Body and BOX Fully Depleted SOI (UTBB FDSOI), and demonstrates the performance gains of this circuit vs. 28nm LP high-κ metal-gate CMOS bulk technology. It also introduces extended body bias (BB) design techniques to take advantage of specific features of the UTBB technology to overcome the +/-300mV BB range limitation of conventional bulk technologies [1]. A chip embedding a family of LDPC decoders has been fabricated in both 28nm LP bulk and 28nm UTBB production processes from STMicroelectronics [2]. The
Philippe Flatresse1, Bastien Giraud2, Jean-Philippe Noel1,