A 27% Reduction in Transceiver Power for Single-Ended Point-to-Point DRAM Interface with the Termination Resistance of 4×Z0 at both TX and RX This integrator helps to reduce power and increase the robustness to highfrequency noise [1, 4-5].

📋 论文概要

本文提出通过将端接电阻提高到4×Z0来降低单端点对点DRAM接口的收发器功耗27%，并采用1-tap和2-tap集成判决反馈均衡器补偿码间干扰和反射，在0.13μm CMOS工艺下实现5Gb/s数据传输，眼图张开度从20%提升至62.5%。

💡 主要创新点

• 将端接电阻提高到4×Z0以降低功耗，同时利用1-tap和2-tap集成判决反馈均衡器（IDFE）分别补偿码间干扰和反射。
• 通过训练模式自动找到反射抽头位置和均衡器系数，无需手动调整。

🏷 关键词

📄 原文摘要

in the single-ended point-to-point DRAM interface by increasing the termination resistance to 4×Z0 at both ends of TX and RX. The resultant increase of ISI and reflection is compensated for at RX by using the 1-tap and 2-tap integrating decision-feedback equalizer (IDFE), respectively, where the reflection tap position and the tap coefficients are found automatically during the training mode. This improves the bathtub opening of a 4-inch FR4 channel from 20% to 62.5% at 5Gb/s in 0.13μm CMOS. As the data rate for the chip-to-chip interface of DRAM reaches several Gb/s, the I/O interface circuit consumes around 20 to 30% of the total chip power. Recently, there is a strong demand for low power in the mobile DRAM interface

👥 作者与机构

Soo-Min Lee1, Jong-Hoon Kim1, Jongsam Kim2, Yunsaing Kim2,

Hyunbae Lee2, Jae-Yoon Sim1, Hong-June Park1 Pohang University of Science and Technology, Pohang, Korea, Hynix Semiconductor, Icheon, Korea 1 2 The transceiver power is reduced by 27%