Cycling Endurance Optimization Scheme for 1Mb STT-MRAM in 40nm Technology

📋 论文概要

该论文针对1Mb STT-MRAM的写耐久性问题，提出了一种带有线电阻平衡方案的新型写路径设计，以减轻MTJ的电压应力，从而优化循环耐久性，满足替代SRAM/DRAM所需的超过10^12次写入要求。

💡 主要创新点

• 提出线电阻平衡方案，均衡不同位线路径的电阻，减少写电压不均匀性导致的MTJ过应力。
• 设计新的写路径结构，通过优化电流路径降低MTJ退化，提升耐久性至10^12次以上。

🏷 关键词

📄 原文摘要

Yu-Der Chih, Tong-Chern Ong, Jonathan Chang, Sreedhar Natarajan, Luan C. Tran TSMC, Hsinchu, Taiwan Spin-transfer-torque (STT) MRAM is considered as a good candidate for nextgeneration memory that can replace Flash, SRAM and DRAM as well. As a replacement of SRAM or DRAM, write endurance more than 1012 cycles is required. However, due to limitation in the reliability of magnetic tunnel junction (MTJ), the required endurance may not be achieved if the MTJ is overstressed by the write voltage. In this paper, a new write-path design with wire-resistancebalance scheme is presented that minimizes the voltage stress on MTJ during write operation for cells near the write buffer. Simulation shows the voltage across MTJ becomes more uniform for cells from top to bottom of array. This new scheme is implemented into 1Mb MRAM test-chip and is fabricated in TSMC 40nm low-power process. Cycling testing shows that write endurance can

👥 作者与机构

Hung-Chang Yu, Kai-Chun Lin, Ku-Feng Lin, Chin-Yi Huang,