3D Clock Distribution Using Vertically/HorizontallyCoupled Resonators

📋 论文概要

该论文提出了一种利用垂直/水平耦合谐振器的3D时钟分布方案，旨在解决高性能微处理器中时钟分配的低偏斜、低抖动和低功耗挑战。通过耦合环形振荡器替代传统H-tree和LC谐振器，有效降低了PVT变化引起的时钟偏斜。

💡 主要创新点

• 提出垂直/水平耦合谐振器结构，实现3D时钟分布，减少芯片面积开销。
• 采用耦合环形振荡器替代LC谐振器，降低时钟偏斜和抖动，无需额外布局面积。

🏷 关键词

📄 原文摘要

Clock distribution with low skew, low jitter, and low power for high-performance microprocessors is a significant design challenge. Although traditional H-tree clock distribution circuits are widely used, the clock skew of such circuits is increased by the PVT variations associated with device scaling [1]. In recent years, there has thus been a growing interest in resonant clock distribution schemes for reduced clock skew. In particular, coupled ring oscillators with shorted outputs [2] can reduce skew and jitter without additional layout area compared to LC resonators [3]. The difference in phase and frequency of each oscillator (due to PVT variations) is equalized by the mutual connection between the oscillators. Power dissipation can also be reduced, as the enhanced variability tolerance may permit operation at lower voltages. In 3D integration, low skew, low jitter, and low power clock distribution is

👥 作者与机构

Yasuhiro Take, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda

Keio University, Yokohama, Japan