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本文提出了一款支持Quad Full HD (3840×2160) 分辨率的HEVC视频解码器芯片，实现了249Mpixel/s的吞吐量。该芯片针对HEVC标准中复杂的编码工具（如可变大小编码单元、大尺寸变换、长插值滤波器）带来的设计挑战，通过系统流水线、存储优化和硬件加速等技术，实现了高效解码。
(HEVC) [1] provides 50% improvement in coding efficiency compared to H.264/AVC, to meet the rising demand for video streaming, better video quality and higher resolutions. The coding gain is achieved using more complex tools such as larger and variable-size coding units (CU) in a hierarchical structure, larger transforms and longer interpolation filters. This paper presents an integrated circuit which supports Quad Full HD (QFHD, 3840×2160) video decoding for the HEVC draft standard. It addresses new design challenges for HEVC (“H.265”) with three primary contributions: 1) a system pipelining scheme which adapts to the variable-size largest coding unit (LCU) and provides a two-stage sub-pipeline for memory optimization; 2) unified processing engines to address the hierarchical coding
Chao-Tsung Huang1, Mehul Tikekar1, Chiraag Juvekar1, Vivienne Sze2, Anantha Chandrakasan1
Massachusetts Institute of Technology, Cambridge, MA, Texas Instruments, Dallas, TX 1 2 The latest video coding standard High Efficiency Video Coding