A 2.5GHz 2.2mW/25μW On/Off-State Power 2psrmsLong-Term-Jitter Digital Clock Multiplier with 3-Reference-Cycles Power-On Time

📋 论文概要

该论文提出了一种数字时钟倍频器，实现了2.5GHz工作频率、2.2mW有源功耗和25μW关断功耗，具有2ps均方根长期抖动，并在3个参考时钟周期内完成上电。主要解决了传统时钟倍频器在功率循环中关断功耗高、上电时间长的问题，以实现能量比例操作。

💡 主要创新点

• 提出了一种基于数字控制的时钟倍频器架构，能够在3个参考时钟周期内快速上电，显著降低功率循环的能量开销。
• 实现了极低的25μW关断功耗，同时保持2.2mW的有源功耗和2ps均方根长期抖动性能，兼顾了高性能与低功耗。
• 通过创新的电路设计，在2.5GHz输出频率下实现了快速启动和低抖动，适用于需要频繁功率循环的节能系统。

🏷 关键词

📄 原文摘要

dissipation and increase battery life. By turning off the circuits that are not in use, power cycling provides a viable means to make power dissipation proportional to workload, hence achieving energy proportional operation. The effectiveness of this approach is governed by the turn on/off times, off-state power dissipation, and energy overhead due to power-cycling. Ideally, the circuits must turn on/off in zero time, consume no off-state power, and incur minimal energy overhead during on-to-off and off-to-on transitions. Conventional clock multipliers implemented using phase-locked loops (PLLs) present the biggest bottleneck in achieving these performance goals due to their long locking times. Even if the PLL is frequency locked, the slow phase acquisition process limits the power-on

👥 作者与机构

Tejasvi Anand, Mrunmay Talegaonkar, Amr Elshazly,

Brian Young, Pavan Kumar Hanumolu Oregon State University, Corvallis, OR Modern mobile platforms utilize power cycling to lower power