A 0.022mm2 970μW Dual-Loop Injection-Locked PLL with -243dB FOM Using Synthesizable All-Digital PVT Calibration Circuits

📋 论文概要

提出一种双环注入锁定PLL，采用可综合的全数字PVT校准电路，实现了0.022mm²面积和970μW低功耗，FOM达-243dB。解决了传统注入锁定PLL在PVT变化下校准困难的问题，降低了时序约束。

💡 主要创新点

• 提出双环注入锁定PLL架构，结合全数字PVT校准电路，实现低面积低功耗。
• 采用可综合的数字校准电路，避免模拟校准的时序约束，提升环境适应性。
• 通过优化设计达到-243dB的优异FOM性能。

🏷 关键词

📄 原文摘要

include low area, low power consumption, environmental insensitivity, and the lowest possible jitter performance. Multiplying Delay-Locked Loop (MDLL) [12], subharmonically injection-locked techniques [3], and sub-sampling techniques [4-5] can significantly improve the random jitter characteristics of a clock generator. However, in order to guarantee their correct operation and optimal performance over process-voltage-temperature (PVT) variations, each method requires additional calibration circuits, which impose difficult-to-meet timing constraints. In the case of an injection-locked PLL (IL-PLL), a free-running frequency calibration is required. However, the output of an injection-locked oscillator is always fixed at the desired frequency, so a shift in the free-running frequency (e.g. caused by temperature and voltage variations) canno

👥 作者与机构

Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara,

Kenichi Okada, Akira Matsuzawa Tokyo Institute of Technology, Tokyo, Japan For modern SoC systems, stringent requirements on on-chip clock generators