A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s Thin-Oxide DDR Transmitter with 1.9-to-7.6V/ns Clock-Feathering Slew-Rate Control in 22nm CMOS impedance levels are controlled by the enable vectors (en_ffe_n/p[3:0] for FFE slices and en_n/p[7:0] for non-FFE slices). Typical impedance ranges are 24 to 40Ω in drive mode and 60 to 240Ω in ODT mode.

📋 论文概要

该论文提出了一种采用薄氧化物器件的DDR发送器，通过时钟羽化压摆率控制实现了1.6Gb/s的数据速率和1.9-7.6V/ns的压摆率范围，同时解决了薄氧化物器件的过压保护问题，显著降低了功耗。

💡 主要创新点

• 使用薄氧化物器件替代厚氧化物器件以降低预驱动器功耗，并通过串联电阻后的晶体管实现过压保护。
• 提出时钟羽化（clock-feathering）技术，实现1.9-7.6V/ns的宽范围压摆率控制。
• 实现了24-240Ω的宽阻抗调节范围和5.7mW/Gb/s的高能效。

🏷 关键词

📄 原文摘要

Matthias Brändli, Peter Buchmann, Lukas Kull, Toke Meyer Andersen, Thomas Morf To save power in the predriver, the SST stages consist of thin-oxide devices, which require overvoltage protection implemented by transistors Mp and Mn following the series-resistors in the SST stack. The gate-bias voltage vprotl for pulldown protection is identical to the predriver supply voltage vddl, whereas the bias voltage vproth for pull-up protection equals vddh-vddl, with vddh being the DC supply of the output stage. Typical values are vddl=vprotl=0.9V, vddh=1.5V, vproth=0.6V. Pull-up protection is generated internally in a vproth generator, which is operated with nonoverlapping clocks from the feathering delay line. It consists of two AC-coupled level shifters (LS1: M1, M2; LS2: M3, M4) and a cross-connected switch (M5, M6) connecting the level-shifted voltage vddh-vddl from LS1 to the integrator capacitor Cv. LS2 is operated with a wider pulse width

👥 作者与机构

Marcel Kossel, Christian Menolfi, Thomas Toifl, Pier Andrea Francese,