A 1/4-inch 8Mpixel Back-Illuminated Stacked CMOS Image Sensor

📋 论文概要

本文提出一款1/4英寸8百万像素背照式堆叠CMOS图像传感器，通过将像素层和电路层垂直堆叠，实现了小尺寸、高像素密度和高速读出，满足了智能手机对多功能和高性能成像的需求。

💡 主要创新点

• 采用背照式（BSI）结构，将光电二极管置于电路层上方，提高了量子效率和感光度。
• 引入堆叠工艺，将像素阵列和信号处理电路分离在不同晶圆上键合，优化了各自工艺并减小芯片面积。

🏷 关键词

📄 原文摘要

Hiroshi Kawanobe1, Ken Koseki2, Isao Hirota1, Tsutomu Haruta1, Masanori Kasai1, Koji Fukumoto1, Toshifumi Wakano1, Keishi Inoue3, Hiroshi Takahashi1, Takashi Nagano1, Yoshikazu Nitta1, Teruo Hirayama1, Noriyuki Fukushima1 Sony, Atsugi, Japan, 2Sony LSI Design, Atsugi, Japan, Sony Semiconductor, Kumamoto, Japan 1 3 In recent years, cellphone cameras have come to require much more diversification and increased functionalities, due to the strong growth of the smartphone market. In addition to the image quality, speed, and pixel counts that conventional image sensors require, there is high demand for new functions that can respond to various photo-taking scenes. We developed a stacked CMOS image sensor (CIS), composed of conventional back-illuminated (BI) image-sensor technology and 65nm standard logic technology. Figure 27.4.1 shows the structure of a stacked BI-CIS, and that of a conventional BI-CIS [1-3]. The stacked BI-CIS uses a logic process substrate instead of the

👥 作者与机构

Shunichi Sukegawa1, Taku Umebayashi1, Tsutomu Nakajima1,