⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文介绍了Oracle SPARC T5处理器，采用28nm工艺，集成了16个核心，运行频率达3.6GHz。通过加倍核心管道数量并改进SoC架构，显著提升了性能、可扩展性和功耗效率。
Dawei Huang, Changku Hwang, Daisy Jian, Tim Johnson, Georgios Konstadinidis, Lance Kwong, Robert Masleid, Umesh Nawathe, Aparna Ramachandran, Yongning Sheng, Jinuk Luke Shin, Sebastian Turullois, Zuxu Qin, King Yen Oracle, Santa Clara, CA The Oracle SPARC T5 [1] processor introduces significant new capabilities in performance, scalability, multi-socket interconnect, power efficiency, and I/O compared to prior CPU generations [2-6]. T5 multiplies T4 [2, 3] performance by doubling the number of core pipes and making a number of architectural improvements in the SoC. A core frequency of 3.6GHz is achieved with enhancements in circuit design, power distribution and clocking coupled with TSMC’s 28nm triple-Vt process. T5 contains 1.5 billion transistors and 13 metal layers. T5 (Fig. 3.2.1) integrates 16 cores, each concurrently executing 8 hardware threads. The cores communicate via a high-bandwidth 9-port crossbar and
Jason Hart, Steve Butler, Hoyeol Cho, Yuefei Ge, Gregory Gruber,