A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit

📋 论文概要

本文提出一种双电源SRAM，利用位线功率计算器（BLPC）和数字可控保持电路（DCRC）在室温至高温范围内降低主动和待机功耗。在28nm CMOS工艺下，测试芯片实现了主动功耗降低27%、待机功耗降低85%的效果。

💡 主要创新点

• 提出位线功率计算器（BLPC），动态调整位线电压以降低主动功耗
• 设计数字可控保持电路（DCRC），在待机时优化保持电压实现85%的待机功耗降低

🏷 关键词

📄 原文摘要

Miyako Shizuno, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa Toshiba, Kawasaki, Japan This paper presents a dual-power-supply SRAM that reduces active and standby power from room temperature (RT) to high temperature (HT) using a BL power calculator (BLPC) and a digitally controllable retention circuit (DCRC). A test-chip is fabricated in a 28nm CMOS technology with a 0.120μm2 6T-SRAM cell. With these schemes, active and standby power consumptions at 25°C are reduced by 27% and 85%, respectively. For a longer battery life, it is important to reduce the power consumption not only in the high-performance mode but also in the low-performance mode, such as MP3 decoding or background processing. As these applications require only tens of MHz operation, the temperature of the chip stays at around RT, where the active and the leakage power consumptions are comparable. Thus, the reduction

👥 作者与机构

Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama,