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本文针对32nm zEnterprise EC12处理器的7GHz L1缓存SRAM设计，采用动态电路应对随机器件变异带来的脉冲收缩和信号对齐问题。提出了新的设计方法以确保在高速和高功耗限制下的可靠运行。
Uma Srinivasan1, Daniel Rodko1, Pradip Patel1, Thomas J. Knips1, Tobias Werner2 IBM, Poughkeepsie, NY, 2IBM, Boeblingen, Germany 1 The L1 cache for the 5.5 GHz 32nm zEnterpriseTM EC12 processor requires SRAM designs that make aggressive use of dynamic circuitry. As technology has scaled and transistor counts have grown, random device variability [1] and power limitations have become significant challenges. In particular, random devicevariability-induced pulse shrinkage and misalignment in dynamic signals must be carefully addressed. Described here are a series of new design approaches enabling L1 cache SRAM operation at 7GHz, including a 3-level bitline hierarchy, decreased dynamic path lengths, localized read enables, and a power-savings mechanism in which selective columns can be partially powered down. The L1 cache is a split-cache design implemented using a data-cache SRAM (dcache), and an instruction-cache SRAM (icache). The dcache is a dual-read 6way set-associative design that f
John D. Davis1, Paul A. Bunce1, Diana M. Henderson1, Yuen H. Chan1,