⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出了一款在65nm低功耗CMOS工艺下实现的视频录制SoC，集成了高效H.264编码器。该芯片在0.48V超低电压下工作，每像素能耗仅为0.57nJ，显著降低了视频录制的功耗。
Po-Hao Wang3, Ting-Yu Shyu1, Chien-Yung Chou2, Shien-Chun Luo2, Jiun-In Guo3, Tien-Fu Chen3, Gene C.H. Chuang2, Yuan-Hua Chu2, Liang-Chia Cheng2, Hong-Men Su4, Chewnpu Jou5, Meikei Ieong5, Cheng-Wen Wu2, Jinn-Shyan Wang1 National Chung Cheng University, Chiayi, Taiwan, Industrial Technology Research Institute, Hsinchu, Taiwan, 3 National Chiao Tung University, Hsinchu, Taiwan, 4 Andes Technology, Hsinchu, Taiwan, 5 TSMC, Hsinchu, Taiwan 1 2 This paper presents a video recording SoC fabricated in 65nm low-power technology, which integrates a complexity and bandwidth-effective H.264 encoder, an ultra-low-power (ULP) MPU, with timing-optimized ROM and 8T SRAM macros for ultra-low-voltage (ULV) operation, a 512Kb ULV and leakage-aware 8T SRAM for the frame buffer (FB), and various on-chip peripherals, such as external memory interfaces (Fig. 9.3.1). Utilizing ULV cell libraries with custompulsed D flip-flops (PFF) for wide-range voltage scaling, ROM/SRAM macros
Tay-Jyi Lin1, Cheng-An Chien1, Pei-Yao Chang1, Ching-Wen Chen2,