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ISSCC 2013Session 3 · PROCESSORSDigital Processors32nm SOI CMOS

GHz System z Microprocessor and Multichip Module

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📋 论文概要

本文介绍了IBM System z微处理器及其多芯片模块(MCM)的设计与实现,旨在解决高性能计算中的功耗、散热和信号完整性等问题。通过创新的微架构和封装技术,实现了GHz级别的运行频率和高集成度。

💡 主要创新点

工艺节点
32nm SOI CMOS
重要性
发表年份
ISSCC 2013

🏷 关键词

微处理器多芯片模块高性能计算

📄 原文摘要

Ruchir Puri4, Sean Carey2, Gerard Salem5, Guenter Mayer3, Yiu-Hing Chan2, Mark Mayo2, Adam Jatkowski2, Gerald Strevig6, Leon Sigal4, Ayan Datta7, Anne Gattiker8, Aditya Bansal4, Douglas Malone2, Thomas Strach3, Huajun Wen6, Pak-Kin Mak2, Chung-Lung Shum2, Donald Plass2, Charles Webb2 IBM Systems and Technology Group, Yorktown Heights, NY, IBM Systems and Technology Group, Poughkeepsie, NY, 3 IBM Systems and Technology Group, Boeblingen, Germany, 4 IBM Research, Yorktown Heights, NY, 5 IBM Systems and Technology Group, Williston, VT, 6 IBM Systems and Technology Group, Austin, TX, 7 IBM Systems and Technology Group, Bangalore, India, 8 IBM Research, Austin, TX 1 2 The new System z microprocessor chip (“CP chip”) features a high-frequency processor core running at 5.5GHz in a 32nm high-κ CMOS technology [1], using 15 levels of metal. This chip is a successor to the 45nm product [2], with significant improvements made to the core and nest (i.e. the logic external to the

👥 作者与机构

James Warnock1, Yuen H Chan2, Hubert Harrer3, David Rude2,

分类:Digital Processors · 年份:ISSCC 2013