A Sub-2W 39.8-to-44.6Gb/s Transmitter and Receiver Chipset with SFI-5.2 Interface in 40nm CMOS

📋 论文概要

本文提出了一款采用40nm CMOS工艺、功耗低于2W、速率范围为39.8至44.6Gb/s的发射机和接收机芯片组，集成了SFI-5.2接口，支持OC-768/OTU-3标准。该芯片组旨在解决互联网基础设施的带宽瓶颈，并通过标准CMOS技术实现以往只有双极工艺才能达到的高速收发性能，同时应对信道带宽限制和接收机抖动容限的挑战。

💡 主要创新点

• 在40nm CMOS工艺上实现了功耗低于2W、速率高达44.6Gb/s的收发器芯片组，突破了传统CMOS在超高速率下的性能限制。

📄 原文摘要

can alleviate bandwidth bottlenecks of Internet infrastructure while simultaneously reducing operating costs. Increasingly, standard CMOS technology is used to enable transceiver speeds [1-5] previously achievable only by using expensive bipolar technology. However, at 40Gb/s, limited channel bandwidth coupled with stringent receiver jitter tolerance requirements demands better solutions than exist currently. In this paper, a TX and RX chipset targeted for a single-lane, line-side data-rate of 39.8 to 44.6Gb/s supporting standards defining the OC-768/OTU-3 interfaces is presented. Additionally, the chipset integrates a host interface that is SFI-5.2

👥 作者与机构

Bharath Raghavan, Delong Cui, Ullas Singh, Hassan Maarefi, Dave Pi,

Anand Vasani, Zhi Huang, Afshin Momtaz, Jun Cao Broadcom, Irvine, CA The introduction of 40Gb/s networks, spurred by 40Gb/s WDM growth,