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本文介绍了第10代SPARC64 X处理器，该处理器采用增强的28nm HKMG CMOS工艺，集成30亿晶体管和588mm²的die，包含16个核心。通过应力控制、SiGe改进和S/D优化实现了约10%的性能提升，面向关键任务UNIX服务器。
Sota Sakabayashi1, Yoichi Koyanagi2, Ryuji Iwatsuki1, Kazumi Hayasaka1, Taiki Uemura3, Gaku Ito1, Yoshitomo Ozeki1, Hiroyuki Adachi1, Kazuhiro Furuya1, Tsuyoshi Motokurumada1 Fujitsu, Kawasaki, Japan, 2Fujitsu Laboratories, Kawasaki, Japan, Fujitsu Semiconductor, Yokohama, Japan 1 3 The 10th generation SPARC64TM processor named SPARC64 X contains 3-billion transistors on a 588mm2 die fabricated in an enhanced 28nm high-κ metal-gate (HKMG) CMOS process, with 13 layers of copper interconnect with low-κ dielectrics. More stress control, SiGe improvement and S/D optimization achieve about 10% higher performance than the standard 28nm high performance (28HP) process. SPARC64 X runs at 3.0GHz and consists of 16 cores, shared 24MB level 2 (L2) cache, four channels of 1.6GHz DDR3 controller, two ports of PCIe Gen3 controller, and five ports of system interface controller. ccNUMA is adopted as its memory system, and a cache coherence control unit for multichip
Ryuji Kan1, Tomohiro Tanaka1, Go Sugizaki1, Ryuichi Nishiyama1,