A Low-Power Radio Chipset in 40nm LP CMOS with Beamforming for 60GHz High-Data-Rate Wireless Communication

📋 论文概要

本文提出了一种在40nm LP CMOS工艺下实现的60GHz低功耗无线芯片组，集成了波束成形技术，用于高速数据传输。通过优化PLL调谐范围和TX增益，解决了毫米波通信中的功耗和性能平衡问题。

💡 主要创新点

• 采用40nm LP CMOS工艺实现了60GHz低功耗射频芯片组，包含波束成形功能。
• 通过调整VCO电感布局，改进了PLL调谐范围（54-63GHz），提高了频率覆盖的灵活性。

🏷 关键词

📄 原文摘要

Giovanni Mangraviti1,2, Steven Brebels1, Wim van Thillo1, Kristof Vaesen1, Bertrand Parvais1, Vadim Issakov1, Mike Libois1, Michiaki Matsuo3, John Long4, Charlotte Soens1, Piet Wambacq1,2 imec, Leuven, Belgium, 2Vrije Universiteit, Brussels, Belgium, Panasonic, Yokohama, Japan, 4 Delft University of Technology, Delft, The Netherlands 1 are limited by the 54GHz to 63GHz PLL tuning range. This is lower than expected due to a slight underestimate of the loading of the prescaler but it can be adapted easily by modifying the VCO’s inductor layout. The maximum TX gain per antenna path is 31dB when the PA operates in ClassA mode with a P1dB of 10.8dBm and a maximum PAE of 33% (see Fig. 13.4.3). Operation at 5dB backoff from P1dB, as required for QAM16 transmission, reduces PAE to 5%. In Class-AB mode, gain and P1dB reduce to 22.5dB and 8dBm, but the PAE at backoff has increased to 7.4%. The 3dB TX RF bandwidth

👥 作者与机构

Vojkan Vidojkovic1, Viki Szortyka1,2, Khaled Khalaf1,2,