A 14b 2.5GS/s 8-Way-Interleaved Pipelined ADC with Background Calibration and Digital Dynamic Linearity Correction the chop PRBS. BUF1 and BUF2 modulate the chop drive signal at the bases of Q1–Q4 with a level-shifted version of the input signal. This bootstrapping ensures that M1 and M2 have a reasonably constant Vgd for improved linearity and reduced thermal transients.

📋 论文概要

本文提出了一种14位2.5GS/s的8路交织流水线ADC，采用背景校准和数字动态线性校正技术。通过模拟抖动作为幅度参考，利用LMS增益校准循环检测输出码与伪随机抖动的相关性，实现片间增益校准，解决了高速高精度ADC中的增益失配和非线性问题。

💡 主要创新点

• 采用模拟抖动作为幅度参考，结合LMS增益校准循环实现片间增益校准，无需中断正常转换。
• 引入数字动态线性校正技术，补偿流水线ADC的非线性误差，提升整体线性度。

🏷 关键词

📄 原文摘要

Valentin Abramzon1, Guenter Steinbach1, John P. Keane1, Bernd Wuppermann1, Mathew Clayson1, Matthew Martin2, Rizwan Pasha2, Edda Peeters3, Annemie Jacobs3, Filip Demarsin3, Adnan Al-Adnani3, Peter Brandt3 The analog dither serves as an amplitude reference for all slices. The LMS gain calibration loops detect any correlation of the output code with the pseudorandom dither after the dither sequence has been subtracted. Slice-to-slice gain calibration is achieved when the gain calibration loops have adjusted all of the slice gain coefficients to minimize any residual dither [4]. Agilent Technologies, Santa Clara, CA, Agilent Technologies, Colorado Springs, CO, 3 Agilent Technologies, Rotselaar, Belgium The chopper enables an offset calibration that correctly converges in the presence of any ADC input signal. Because the chopper is driven with a zero-mean PRBS, calibration is achieved when the offset calibration loops converge to coefficients that produce a slice digital output that also h

👥 作者与机构

Brian Setterberg1, Ken Poulton1, Sourja Ray1, Dan J. Huber1,