A 20nm 112Mb SRAM in High-κ Metal-Gate with Assist Circuitry for Low-Leakage and Low-VMIN Applications

📋 论文概要

本文在20nm高k金属栅极工艺上实现了112Mb SRAM，通过辅助电路技术有效降低了漏电流和最小工作电压（Vmin），适用于低功耗和低电压的SoC平台应用。

💡 主要创新点

• 采用20nm高k金属栅极工艺，实现了面积小于0.1μm²的高密度和高性能SRAM位单元。
• 设计了辅助电路（如读写辅助、电压调节等）以降低漏电和Vmin，提升低电压下的稳定性。
• 针对SoC平台优化了工艺和电路，兼顾低功耗与高性能需求。

🏷 关键词

📄 原文摘要

Hung-Jen Liao, Quincy Li, Stanley Chang, Sreedhar Natarajan, Robin Lee, Ping-Wei Wang, Shyue-Shyh Lin, Chung-Cheng Wu, Kuan-Lun Cheng, Min Cao, George H. Chang TSMC, Hsinchu, Taiwan A 20nm high-κ metal-gate planar CMOS technology is optimized and developed for SoC platform applications that span a wide range of power and performance. This technology is based on a 20nm SoC process featuring high-κ metal gate and strain techniques for core logic transistors with low-power/high-performance and I/O transistors. A high-density and a high-performance embedded memory bit cell each has an area <0.1μm2. This technology is targeted to highdensity low-cost low-power high-performance applications, such as mobile applications with video. Increased threshold-voltage variation of scaled transistors reduces the static noise margin (SNM) and write margin (WM) of the SRAM bit cell. The effect is more predominant for the high-density SRAMs due to small

👥 作者与机构

Jonathan Chang, Yen-Huei Chen, Hank Cheng, Wei-Min Chan,