A 1.7mW 0.22mm2 2.4GHz ZigBee RX Exploiting a Current-Reuse Blixer + Hybrid Filter Topology in 65nm CMOS

📋 论文概要

该论文提出了一款基于65nm CMOS工艺的2.4GHz ZigBee接收机，通过采用电流复用Blixer和混合滤波器拓扑，实现了1.7mW功耗和0.22mm2芯片面积。同时，设计了一种0.6V供电的LO发生器，利用电容分压降低等效负载，优化了混频器的增益和噪声系数。

💡 主要创新点

• 提出电流复用Blixer结构，将混频器和滤波器功能结合，降低功耗和面积。
• 采用混合滤波器拓扑，提高接收机选择性并减少外部元件。
• 设计0.6V低电压LO发生器，通过电容分压实现最优LO幅度，降低功耗。

🏷 关键词

📄 原文摘要

Instituto Superior Tecnico, Lisbon, Portugal 1 A GHz-range div-by-2 is compact and wideband enough to generate a 4-phase LO with a duty cycle not necessarily 50%. Here, DIV1 accepts a 50%-duty-cycle 2-phase input, and delivers a 25%-duty-cycle 4-phase output. To save power, the LO generator is designed at a 0.6V supply. Since an LO amplitude of ~0.4Vpp is optimum for the mixing in terms of gain and NF, while the buffered LO is as high as 0.6Vpp, CLO was added to create a capacitor divider with CMIX,in (input capacitance of the mixer). This act brings down the equivalent load (CL,eq) of the LO buffer by ~33% for power savings. 2 Nanoscale CMOS offers sufficiently high ft and low Vt favoring the design of ultra-low-power wireless receivers (RX) via stacking the RF-to-BB functions in one cell, while sharing the smallest possible bias current. Also, the signals can be conveyed in the current domain to enhance the area efficiency (i.e., no ACcoupling capacitor), RF bandwidth and linearity a

👥 作者与机构

Zhicheng Lin1, Pui-In Mak1, Rui Martins1,2

University of Macau, Macao, China,