A 32-to-48Gb/s Serializing Transmitter Using Multiphase Sampling in 65nm CMOS

📋 论文概要

本文提出了一种采用多相采样技术的32-48Gb/s串行发射机，在65nm CMOS工艺中实现。该设计消除了传统串行器中最后一级的建立/保持时间约束，避免了延迟匹配缓冲器或校准环路，从而降低了功耗和面积开销。

💡 主要创新点

• 利用多相采样技术替代传统高速串行器的最后一级多路复用，放宽了定时约束，支持更宽的工作速率范围。
• 无需延迟匹配或校准电路，在PVT变化下自动满足时序要求，降低了复杂度。

🏷 关键词

📄 原文摘要

Serial-link transmitters are widely used in applications like optical transceivers and multi-gigabit Ethernet. At tens of Gb/s, the operating range of bit-rates is narrow; limited by the speed of the multiplexing and the setup and hold time constraints of the last stage in the serializer. This constraint leads to using delaymatching buffers [1] or delay calibration loops [1-2] to guarantee that timing constraints are always met at the desired bit-rate across all PVT corners. This additional circuitry increases power, area, and overall complexity of the transmitter. The timing constraint and power penalty are particularly severe when the data rate is high compared to the inherent speed of the technology. Our transmitter design introduces a multiplexing tree with a high-speed final multiplexing stage that uses multiphase sampling with optimum phase shifts between the triggering and the sampling clock edges. The phases are chosen to

👥 作者与机构

Amr Amin Hafez, Ming-Shuan Chen, Chih-Kong Ken Yang

University of California, Los Angeles, CA