A Blind Baud-Rate ADC-Based CDR

📋 论文概要

本文提出了一种基于盲波特率ADC的时钟数据恢复(CDR)电路，通过数字域处理接收数据，减少了对模拟前端的需求。该设计解决了时钟偏斜导致的抖动和增益失配问题，并采用可变延迟补偿技术。

💡 主要创新点

• 采用盲波特率ADC实现CDR，无需模拟锁相环，简化了接收机架构。
• 通过可变延迟补偿时钟偏斜，有效抑制了高频周期性抖动和增益失配。

🏷 关键词

📄 原文摘要

ter tolerance degradation in one of two ways. First, clock skew would appear effectively as high-frequency periodic jitter. Second, the interleaved I&D blocks would experience a gain mismatch because the integration is performed over the pulse width. For these reasons, a variable delay of up to 20ps is included in each of the four CML-to-CMOS converters in order to compensate for clock skew. University of Toronto, Toronto, Canada, 2Fujitsu Laboratories, Kawasaki, Japan 1 ADC-based receivers process the received data in the digital domain, eliminating the need for much of the analog front end. In addition, a feed-forward blind architecture [1,2] eliminates the feedback loop between digital and analog domains so that the ADC and digital CDR can be designed and simulated independently. Previous works [1,2] sampled the incoming data at 2 samples per UI and at 1.45 samples per UI to achieve 5Gb/s and 6.875Gb/s, respectively. To further increase the data rate to 10Gb/s, we sample at baud rat

👥 作者与机构

Clifford Ting1, Joshua Liang1, Ali Sheikholeslami1, Masaya Kibune2, Hirotaka Tamura2